VPGATHERDD (YMM, VSIB_YMM, YMM) - Latency


Operands


Latency operand 1 → 1: 14

Latency operand 1 → 3: 7

Latency operand 2 → 1 (address, base register): ≤20

Latency operand 2 → 1 (address, index register): ≤23

Latency operand 2 → 1 (memory): ≤12

Latency operand 2 → 3 (address, base register): ≤4

Latency operand 2 → 3 (address, index register): ≤8

Latency operand 2 → 3 (memory): ≤1

Latency operand 3 → 1: 20

Latency operand 3 → 3: 7


Latency operand 1 → 1: 14

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)


Latency operand 1 → 3: 7

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, base register): ≤20

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, index register): ≤23

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (memory): ≤12

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (address, base register): ≤4

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (address, index register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (memory): ≤1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1: 20

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 3: 7

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)