VPCOMPRESSD (M512, K, ZMM)

Operands

• Operand 1 (w): Memory
• Operand 2 (r): Register (K1, K2, K3, K4, K5, K6, K7)
• Operand 3 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 3 → 1: ≤8
• Throughput
  • Computed from the port usage: 2.00 (if an indexed addressing mode is used: 0.50)
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p49+2*p5+1*p78 (if an indexed addressing mode is used: 1*p49+1*p78)

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p49+2*p5+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p49+2*p5+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p49+2*p5+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p237+1*p4+2*p5 (if an indexed addressing mode is used: 1*p23+1*p4+2*p5)

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p237+1*p4+2*p5 (if an indexed addressing mode is used: 1*p23+1*p4+2*p5)

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 3 → 1: ≤15
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p237+1*p4+2*p5 (if an indexed addressing mode is used: 1*p23+1*p4+2*p5)
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 4
• Port usage: 1*p237+1*p4+2*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.96
• Number of μops: 4
• Port usage: 1*p237+1*p4+2*p5

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤52
  • Latency operand 1 → 1 (address, index register): ≤51
  • Latency operand 3 → 1: ≤40
• Throughput
  • Computed from the port usage: 9.00
  • Measured (loop): 72.50
  • Measured (unrolled): 72.50
• Number of μops
  • Executed: 144
• Port usage: 1*FP01+1*FP12+2*FP23+18*FP45