VPCOMPRESSD (M512, K, ZMM)

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥6

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 18.05
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 10.98

Experiment 2 (with additional nop)

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥6

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 18.06
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 11.01

Latency operand 1 → 1 (address, index register): ≤12

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14+R13] {K1}, ZMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥6

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 18.06
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 10.99

Experiment 2 (with additional nop)

Instruction: VPCOMPRESSD zmmword ptr [R14+R13] {K1}, ZMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥6

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12
  1d:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 18.06
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 10.97

Latency operand 3 → 1: ≤8

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: VMOVUPD XMM13, [R14];VSHUFPD XMM0, XMM13, XMM13, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: ≥6

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	c4 41 79 10 2e       	vmovupd xmm13,XMMWORD PTR [r14]
   b:	c4 c1 11 c6 c5 00    	vshufpd xmm0,xmm13,xmm13,0x0
  11:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  16:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  20:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.43
- Reference cycles: 11.52
- UOPS_EXECUTED.THREAD: 9.99

Experiment 2

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: VMOVDQU XMM13, [R14];VPAND XMM0, XMM13, XMM13;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: ≥6

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	c4 41 7a 6f 2e       	vmovdqu xmm13,XMMWORD PTR [r14]
   b:	c4 c1 11 db c5       	vpand  xmm0,xmm13,xmm13
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  18:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.62
- Reference cycles: 10.56
- UOPS_EXECUTED.THREAD: 9.99

VPCOMPRESSD (M512, K, ZMM) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤12

Latency operand 1 → 1 (address, index register): ≤12

Latency operand 3 → 1: ≤8

Latency operand 1 → 1 (address, base register): ≤12

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤12

Experiment 1

Experiment 2 (with additional nop)

Latency operand 3 → 1: ≤8

Experiment 1

Experiment 2