VPCOMPRESSD (M512, K, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.99
- UOPS_MITE: 5.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.05
- Reference cycles: 2.74
- UOPS_EXECUTED.THREAD: 16.03
- RETIRE_SLOTS: 11.97
- UOPS_MITE: 12.04
- UOPS_MS: 0.12
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_5: 7.99
- UOPS_PORT_6: -0.02
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.14
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.1
- Reference cycles: 5.48
- UOPS_EXECUTED.THREAD: 32.05
- RETIRE_SLOTS: 23.97
- UOPS_MITE: 24.08
- UOPS_MS: 0.24
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_5: 15.97
- UOPS_PORT_6: -0.04
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 5.46
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 25.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 5.46
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.25
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	02 00 00 
  41:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x240]{k1},zmm0
  48:	02 00 00 
  4b:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x280]{k1},zmm0
  52:	02 00 00 
  55:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  5c:	02 00 00 
  5f:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x300]{k1},zmm0
  66:	03 00 00 
  69:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x340]{k1},zmm0
  70:	03 00 00 
  73:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x380]{k1},zmm0
  7a:	03 00 00 
  7d:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x3c0]{k1},zmm0
  84:	03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.1
- Reference cycles: 10.85
- UOPS_EXECUTED.THREAD: 64.05
- RETIRE_SLOTS: 47.94
- UOPS_MITE: 48.0
- UOPS_MS: 0.24
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.02
- UOPS_PORT_5: 31.99
- UOPS_PORT_6: -0.04
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	02 00 00 
  41:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x240]{k1},zmm0
  48:	02 00 00 
  4b:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x280]{k1},zmm0
  52:	02 00 00 
  55:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  5c:	02 00 00 
  5f:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x300]{k1},zmm0
  66:	03 00 00 
  69:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x340]{k1},zmm0
  70:	03 00 00 
  73:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x380]{k1},zmm0
  7a:	03 00 00 
  7d:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x3c0]{k1},zmm0
  84:	03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 10.91
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.05
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d2 7d 49 8b 46 10 	vpcompressd ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d2 7d 49 8b 46 20 	vpcompressd ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d2 7d 49 8b 46 30 	vpcompressd ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d2 7d 49 8b 46 40 	vpcompressd ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d2 7d 49 8b 46 50 	vpcompressd ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d2 7d 49 8b 46 60 	vpcompressd ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d2 7d 49 8b 46 70 	vpcompressd ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	02 00 00 
  41:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x240]{k1},zmm0
  48:	02 00 00 
  4b:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x280]{k1},zmm0
  52:	02 00 00 
  55:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  5c:	02 00 00 
  5f:	62 d2 7d 49 8b 86 00 	vpcompressd ZMMWORD PTR [r14+0x300]{k1},zmm0
  66:	03 00 00 
  69:	62 d2 7d 49 8b 86 40 	vpcompressd ZMMWORD PTR [r14+0x340]{k1},zmm0
  70:	03 00 00 
  73:	62 d2 7d 49 8b 86 80 	vpcompressd ZMMWORD PTR [r14+0x380]{k1},zmm0
  7a:	03 00 00 
  7d:	62 d2 7d 49 8b 86 c0 	vpcompressd ZMMWORD PTR [r14+0x3c0]{k1},zmm0
  84:	03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 10.91
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.49
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.99
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.95
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 2.74
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.12
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.11
- Reference cycles: 5.37
- UOPS_EXECUTED.THREAD: 32.05
- RETIRE_SLOTS: 23.97
- UOPS_MITE: 24.08
- UOPS_MS: 0.24
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_5: 15.97
- UOPS_PORT_6: -0.04
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 5.45
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 25.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.02
- Reference cycles: 5.46
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.25
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70 
  3f:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	00 02 00 00 
  4a:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  51:	40 02 00 00 
  55:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  5c:	80 02 00 00 
  60:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  67:	c0 02 00 00 
  6b:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  72:	00 03 00 00 
  76:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  7d:	40 03 00 00 
  81:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  88:	80 03 00 00 
  8c:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  93:	c0 03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.13
- Reference cycles: 10.85
- UOPS_EXECUTED.THREAD: 64.05
- RETIRE_SLOTS: 47.94
- UOPS_MITE: 48.08
- UOPS_MS: 0.24
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_5: 31.97
- UOPS_PORT_6: -0.04
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70 
  3f:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	00 02 00 00 
  4a:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  51:	40 02 00 00 
  55:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  5c:	80 02 00 00 
  60:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  67:	c0 02 00 00 
  6b:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  72:	00 03 00 00 
  76:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  7d:	40 03 00 00 
  81:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  88:	80 03 00 00 
  8c:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  93:	c0 03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 10.92
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.06
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	10 
   f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	20 
  17:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	30 
  1f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	40 
  27:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	50 
  2f:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	60 
  37:	62 92 7d 49 8b 44 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	70 
  3f:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	00 02 00 00 
  4a:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  51:	40 02 00 00 
  55:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  5c:	80 02 00 00 
  60:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  67:	c0 02 00 00 
  6b:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  72:	00 03 00 00 
  76:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  7d:	40 03 00 00 
  81:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  88:	80 03 00 00 
  8c:	62 92 7d 49 8b 84 2e 	vpcompressd ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  93:	c0 03 00 00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 10.91
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.49
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VPCOMPRESSD (M512, K, ZMM) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10