VCVTPS2PD (ZMM, YMM)

Summary:	"Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values"
Reference:	https://www.felixcloutier.com/x86/CVTPS2PD.html
Extension:	AVX512EVEX
Category:	CONVERT
ISA-Set:	AVX512F_512
CPL:	3
iform:	VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
iclass:	VCVTPS2PD
ASM:	VCVTPS2PD

Operands

Operand 1 (w): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.00
- Measured (unrolled): 1.00
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.00
- Measured (unrolled): 1.00
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.00
- Measured (unrolled): 1.00
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.00
- Measured (unrolled): 1.00
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.08
- Measured (unrolled): 1.11
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p05+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.00
- Measured (unrolled): 1.00
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p5

Latencies
- Latency operand 2 → 1: 7
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 1.09
- Measured (unrolled): 1.11
Number of μops
- Executed: 2
- Retire slots: 2
- Decoded (MITE): 2
- Microcode Sequencer (MS): 0
- Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage: 1*p05+1*p5

Latencies
- Latency operand 2 → 1: 6
Throughput
- Computed from the port usage: 0.67
- Measured (loop): 1.33
- Measured (unrolled): 1.33
Number of μops
- Executed: 2
Port usage: 1*FP12+1*FP23