VCVTPS2PD (ZMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.52
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.59
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.55
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.12
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.12

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.51
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.51
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 1.82
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.04
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.03
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 4.06
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 4.07
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1
  30:	62 71 7c 48 5a c9    	vcvtps2pd zmm9,ymm1
  36:	62 71 7c 48 5a d1    	vcvtps2pd zmm10,ymm1
  3c:	62 71 7c 48 5a d9    	vcvtps2pd zmm11,ymm1
  42:	62 71 7c 48 5a e1    	vcvtps2pd zmm12,ymm1
  48:	62 e1 7c 48 5a c1    	vcvtps2pd zmm16,ymm1
  4e:	62 e1 7c 48 5a c9    	vcvtps2pd zmm17,ymm1
  54:	62 e1 7c 48 5a d1    	vcvtps2pd zmm18,ymm1
  5a:	62 e1 7c 48 5a d9    	vcvtps2pd zmm19,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 7.45
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1
  30:	62 71 7c 48 5a c9    	vcvtps2pd zmm9,ymm1
  36:	62 71 7c 48 5a d1    	vcvtps2pd zmm10,ymm1
  3c:	62 71 7c 48 5a d9    	vcvtps2pd zmm11,ymm1
  42:	62 71 7c 48 5a e1    	vcvtps2pd zmm12,ymm1
  48:	62 e1 7c 48 5a c1    	vcvtps2pd zmm16,ymm1
  4e:	62 e1 7c 48 5a c9    	vcvtps2pd zmm17,ymm1
  54:	62 e1 7c 48 5a d1    	vcvtps2pd zmm18,ymm1
  5a:	62 e1 7c 48 5a d9    	vcvtps2pd zmm19,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 8.15
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.01
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c1    	vcvtps2pd zmm0,ymm1
   6:	62 f1 7c 48 5a d1    	vcvtps2pd zmm2,ymm1
   c:	62 f1 7c 48 5a d9    	vcvtps2pd zmm3,ymm1
  12:	62 f1 7c 48 5a e1    	vcvtps2pd zmm4,ymm1
  18:	62 f1 7c 48 5a e9    	vcvtps2pd zmm5,ymm1
  1e:	62 f1 7c 48 5a f1    	vcvtps2pd zmm6,ymm1
  24:	62 f1 7c 48 5a f9    	vcvtps2pd zmm7,ymm1
  2a:	62 71 7c 48 5a c1    	vcvtps2pd zmm8,ymm1
  30:	62 71 7c 48 5a c9    	vcvtps2pd zmm9,ymm1
  36:	62 71 7c 48 5a d1    	vcvtps2pd zmm10,ymm1
  3c:	62 71 7c 48 5a d9    	vcvtps2pd zmm11,ymm1
  42:	62 71 7c 48 5a e1    	vcvtps2pd zmm12,ymm1
  48:	62 e1 7c 48 5a c1    	vcvtps2pd zmm16,ymm1
  4e:	62 e1 7c 48 5a c9    	vcvtps2pd zmm17,ymm1
  54:	62 e1 7c 48 5a d1    	vcvtps2pd zmm18,ymm1
  5a:	62 e1 7c 48 5a d9    	vcvtps2pd zmm19,ymm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.02
- Reference cycles: 8.11
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.0
- Reference cycles: 3.56
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.0
- Reference cycles: 3.56
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.0
- Reference cycles: 3.73
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.01
- Reference cycles: 3.56
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.01
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 3.47
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 4.09
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 4.09
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7
  30:	62 51 7c 48 5a c0    	vcvtps2pd zmm8,ymm8
  36:	62 51 7c 48 5a c9    	vcvtps2pd zmm9,ymm9
  3c:	62 51 7c 48 5a d2    	vcvtps2pd zmm10,ymm10
  42:	62 51 7c 48 5a db    	vcvtps2pd zmm11,ymm11
  48:	62 51 7c 48 5a e4    	vcvtps2pd zmm12,ymm12
  4e:	62 a1 7c 48 5a c0    	vcvtps2pd zmm16,ymm16
  54:	62 a1 7c 48 5a c9    	vcvtps2pd zmm17,ymm17
  5a:	62 a1 7c 48 5a d2    	vcvtps2pd zmm18,ymm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 7.97
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 31.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7
  30:	62 51 7c 48 5a c0    	vcvtps2pd zmm8,ymm8
  36:	62 51 7c 48 5a c9    	vcvtps2pd zmm9,ymm9
  3c:	62 51 7c 48 5a d2    	vcvtps2pd zmm10,ymm10
  42:	62 51 7c 48 5a db    	vcvtps2pd zmm11,ymm11
  48:	62 51 7c 48 5a e4    	vcvtps2pd zmm12,ymm12
  4e:	62 a1 7c 48 5a c0    	vcvtps2pd zmm16,ymm16
  54:	62 a1 7c 48 5a c9    	vcvtps2pd zmm17,ymm17
  5a:	62 a1 7c 48 5a d2    	vcvtps2pd zmm18,ymm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 8.13
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7c 48 5a c0    	vcvtps2pd zmm0,ymm0
   6:	62 f1 7c 48 5a c9    	vcvtps2pd zmm1,ymm1
   c:	62 f1 7c 48 5a d2    	vcvtps2pd zmm2,ymm2
  12:	62 f1 7c 48 5a db    	vcvtps2pd zmm3,ymm3
  18:	62 f1 7c 48 5a e4    	vcvtps2pd zmm4,ymm4
  1e:	62 f1 7c 48 5a ed    	vcvtps2pd zmm5,ymm5
  24:	62 f1 7c 48 5a f6    	vcvtps2pd zmm6,ymm6
  2a:	62 f1 7c 48 5a ff    	vcvtps2pd zmm7,ymm7
  30:	62 51 7c 48 5a c0    	vcvtps2pd zmm8,ymm8
  36:	62 51 7c 48 5a c9    	vcvtps2pd zmm9,ymm9
  3c:	62 51 7c 48 5a d2    	vcvtps2pd zmm10,ymm10
  42:	62 51 7c 48 5a db    	vcvtps2pd zmm11,ymm11
  48:	62 51 7c 48 5a e4    	vcvtps2pd zmm12,ymm12
  4e:	62 a1 7c 48 5a c0    	vcvtps2pd zmm16,ymm16
  54:	62 a1 7c 48 5a c9    	vcvtps2pd zmm17,ymm17
  5a:	62 a1 7c 48 5a d2    	vcvtps2pd zmm18,ymm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.02
- Reference cycles: 8.11
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VCVTPS2PD (ZMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10