RCL (R64, CL)

Operands

• Operand 1 (r/w): Register (RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15)
• Operand 2 (r): Register (CL)
• Operand 3 (r/w, suppressed): Flags (CF: r/cw, OF: undef)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 5.91
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 5
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156B+3*p06+2*p1

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1: 7
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 9
  • Latency operand 2 → 3: 9
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 6
• Throughput
  • Measured (loop): 9.75
  • Measured (unrolled): 10.98
• Number of μops
  • Executed: 14
  • Microcode Sequencer (MS): 13
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 5
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+3*p06+2*p1

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 5
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+3*p06+2*p1

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 5
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+3*p06+2*p1

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 7
• Port usage: 2*p0156+3*p06+2*p1
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.99
• Number of μops: 7
• Port usage: 2*p0156+3*p06+2*p1

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 7
• Port usage: 2*p0156+3*p06+2*p1
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.99
• Number of μops: 7
• Port usage: 2*p0156+3*p06+2*p1

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 7.00)
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.99
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 7
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 8
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 7
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+4*p06+2*p1
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 5.95)
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.99
• Number of μops: 7
• Port usage: 3*p0156+2*p06+2*p1

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 1 → 3: 5
  • Latency operand 2 → 1: 5
  • Latency operand 2 → 3: 6
  • Latency operand 3 → 1: 4
  • Latency operand 3 → 3: 5
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p015+4*p05+1*p1+1*p5

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 1 → 3: 5
  • Latency operand 2 → 1: 5
  • Latency operand 2 → 3: 6
  • Latency operand 3 → 1: 4
  • Latency operand 3 → 3: 5
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p015+4*p05+1*p1+1*p5

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 13
  • Latency operand 2 → 1: 7
  • Latency operand 2 → 3: 14
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 13
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 6
  • Retire slots: 6
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder
• Port usage: 3*p015+1*p05+2*p1

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1: 6
  • Latency operand 1 → 3: 13
  • Latency operand 2 → 1: 5
  • Latency operand 2 → 3: 12
  • Latency operand 3 → 1: 6
  • Latency operand 3 → 3: 13
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 6
  • Retire slots: 6
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder
• Port usage: 3*p015+1*p05+2*p1

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1: 3
  • Latency operand 1 → 3: 11
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 9
  • Latency operand 3 → 1: 4
  • Latency operand 3 → 3: 9
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 6
• Port usage: 2*p015+2*p05+1*p1+1*p5

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1: 3
  • Latency operand 1 → 3: 11
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 9
  • Latency operand 3 → 1: 3
  • Latency operand 3 → 3: 9
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 6
• Port usage: 2*p015+2*p05+1*p1+1*p5

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1: 8
  • Latency operand 1 → 3: 9
  • Latency operand 2 → 1: 10
  • Latency operand 2 → 3: 10
  • Latency operand 3 → 1: 7
  • Latency operand 3 → 3: 7
• Throughput
  • Measured (loop): 13.00
  • Measured (unrolled): 13.00
• Number of μops
  • Executed: 17
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1: 8
  • Latency operand 1 → 3: 8
  • Latency operand 2 → 1: 9
  • Latency operand 2 → 3: 10
  • Latency operand 3 → 1: 7
  • Latency operand 3 → 3: 7
• Throughput
  • Measured (loop): 15.00
  • Measured (unrolled): 15.00
• Number of μops
  • Executed: 15
  • Microcode Sequencer (MS): 15
  • Requires the complex decoder

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1: 11
  • Latency operand 1 → 3: 12
  • Latency operand 2 → 1: 11
  • Latency operand 2 → 3: 11
  • Latency operand 3 → 1: 10
  • Latency operand 3 → 3: 9
• Throughput
  • Measured (loop): 16.00
  • Measured (unrolled): 16.00
• Number of μops
  • Executed: 16
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1: 8
  • Latency operand 1 → 3: 8
  • Latency operand 2 → 1: 10
  • Latency operand 2 → 3: 12
  • Latency operand 3 → 1: 8
  • Latency operand 3 → 3: 8
• Throughput
  • Measured (loop): 12.00
  • Measured (unrolled): 12.00
• Number of μops
  • Executed: 13
  • Microcode Sequencer (MS): 13
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1: 13
  • Latency operand 1 → 3: 13
  • Latency operand 2 → 1: 13
  • Latency operand 2 → 3: 13
  • Latency operand 3 → 1: 13
  • Latency operand 3 → 3: 13
• Throughput
  • Measured (loop): 14.00
  • Measured (unrolled): 14.00
• Number of μops
  • Executed: 14
  • Microcode Sequencer (MS): 14
  • Requires the complex decoder

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 2
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 3
  • Latency operand 3 → 1: 2
  • Latency operand 3 → 3: 2
• Throughput
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 9

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 2
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 3
  • Latency operand 3 → 1: 2
  • Latency operand 3 → 3: 2
• Throughput
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 9
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU1/2

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 2
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 3
  • Latency operand 3 → 1: 2
  • Latency operand 3 → 3: 2
• Throughput
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 9
• Documentation
• Latency: 1
• Throughput: 0.25
• Number of μops: 1
• Port usage: ALU

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 2
  • Latency operand 2 → 1: 3
  • Latency operand 2 → 3: 4
  • Latency operand 3 → 1: 2
  • Latency operand 3 → 3: 2
• Throughput
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 9
• Documentation
• Latency: 1
• Throughput: 0.25
• Number of μops: 1
• Port usage: ALU