RCL (R64, CL) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c1          	movd   r9d,mm0
   4:	41 0f 7e c2          	movd   r10d,mm0
   8:	41 0f 7e c3          	movd   r11d,mm0
   c:	41 0f 7e c4          	movd   r12d,mm0
  10:	0f 7e c3             	movd   ebx,mm0
  13:	0f 7e c2             	movd   edx,mm0
  16:	41 0f 7e c1          	movd   r9d,mm0
  1a:	41 0f 7e c2          	movd   r10d,mm0
  1e:	41 0f 7e c3          	movd   r11d,mm0
  22:	41 0f 7e c4          	movd   r12d,mm0
  26:	0f 7e c3             	movd   ebx,mm0
  29:	0f 7e c2             	movd   edx,mm0
  2c:	41 0f 7e c1          	movd   r9d,mm0
  30:	41 0f 7e c2          	movd   r10d,mm0
  34:	49 d3 d0             	rcl    r8,cl

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.07
- Reference cycles: 12.62
- UOPS_PORT_0: 14.01

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	49 d3 d0             	rcl    r8,cl

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 16.14
- Reference cycles: 14.42
- UOPS_PORT_1: 16.0

⇨ 2 μops that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  3b:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  41:	66 0f 38 de c1       	aesdec xmm0,xmm1
  46:	66 0f 38 de d1       	aesdec xmm2,xmm1
  4b:	49 d3 d0             	rcl    r8,cl

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.17
- Reference cycles: 12.62
- UOPS_PORT_5: 13.99

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 59 c1          	mulpd  xmm0,xmm1
   4:	66 0f 59 d1          	mulpd  xmm2,xmm1
   8:	66 0f 59 d9          	mulpd  xmm3,xmm1
   c:	66 0f 59 e1          	mulpd  xmm4,xmm1
  10:	66 0f 59 e9          	mulpd  xmm5,xmm1
  14:	66 0f 59 f1          	mulpd  xmm6,xmm1
  18:	66 0f 59 f9          	mulpd  xmm7,xmm1
  1c:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  21:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  26:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  2b:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  30:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  35:	66 0f 59 c1          	mulpd  xmm0,xmm1
  39:	66 0f 59 d1          	mulpd  xmm2,xmm1
  3d:	66 0f 59 d9          	mulpd  xmm3,xmm1
  41:	66 0f 59 e1          	mulpd  xmm4,xmm1
  45:	66 0f 59 e9          	mulpd  xmm5,xmm1
  49:	66 0f 59 f1          	mulpd  xmm6,xmm1
  4d:	66 0f 59 f9          	mulpd  xmm7,xmm1
  51:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  56:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  5b:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  60:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  65:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  6a:	66 0f 59 c1          	mulpd  xmm0,xmm1
  6e:	66 0f 59 d1          	mulpd  xmm2,xmm1
  72:	66 0f 59 d9          	mulpd  xmm3,xmm1
  76:	66 0f 59 e1          	mulpd  xmm4,xmm1
  7a:	49 d3 d0             	rcl    r8,cl

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 15.29
- Reference cycles: 13.56
- UOPS_PORT_1: 15.03
- UOPS_PORT_0: 14.94

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c1 00       	rol    r9w,0x0
   5:	66 41 c1 c2 00       	rol    r10w,0x0
   a:	66 41 c1 c3 00       	rol    r11w,0x0
   f:	66 41 c1 c4 00       	rol    r12w,0x0
  14:	66 c1 c3 00          	rol    bx,0x0
  18:	66 c1 c2 00          	rol    dx,0x0
  1c:	66 41 c1 c1 00       	rol    r9w,0x0
  21:	66 41 c1 c2 00       	rol    r10w,0x0
  26:	66 41 c1 c3 00       	rol    r11w,0x0
  2b:	66 41 c1 c4 00       	rol    r12w,0x0
  30:	66 c1 c3 00          	rol    bx,0x0
  34:	66 c1 c2 00          	rol    dx,0x0
  38:	66 41 c1 c1 00       	rol    r9w,0x0
  3d:	66 41 c1 c2 00       	rol    r10w,0x0
  42:	66 41 c1 c3 00       	rol    r11w,0x0
  47:	66 41 c1 c4 00       	rol    r12w,0x0
  4c:	66 c1 c3 00          	rol    bx,0x0
  50:	66 c1 c2 00          	rol    dx,0x0
  54:	66 41 c1 c1 00       	rol    r9w,0x0
  59:	66 41 c1 c2 00       	rol    r10w,0x0
  5e:	66 41 c1 c3 00       	rol    r11w,0x0
  63:	66 41 c1 c4 00       	rol    r12w,0x0
  68:	66 c1 c3 00          	rol    bx,0x0
  6c:	66 c1 c2 00          	rol    dx,0x0
  70:	66 41 c1 c1 00       	rol    r9w,0x0
  75:	66 41 c1 c2 00       	rol    r10w,0x0
  7a:	66 41 c1 c3 00       	rol    r11w,0x0
  7f:	66 41 c1 c4 00       	rol    r12w,0x0
  84:	49 d3 d0             	rcl    r8,cl

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 16.23
- Reference cycles: 14.63
- UOPS_PORT_6: 15.94
- UOPS_PORT_0: 16.03

⇨ 4 μops that can only use ports {'0', '6'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 0e             	lea    r9d,[r14]
   3:	45 8d 16             	lea    r10d,[r14]
   6:	45 8d 1e             	lea    r11d,[r14]
   9:	45 8d 26             	lea    r12d,[r14]
   c:	41 8d 1e             	lea    ebx,[r14]
   f:	41 8d 16             	lea    edx,[r14]
  12:	45 8d 0e             	lea    r9d,[r14]
  15:	45 8d 16             	lea    r10d,[r14]
  18:	45 8d 1e             	lea    r11d,[r14]
  1b:	45 8d 26             	lea    r12d,[r14]
  1e:	41 8d 1e             	lea    ebx,[r14]
  21:	41 8d 16             	lea    edx,[r14]
  24:	45 8d 0e             	lea    r9d,[r14]
  27:	45 8d 16             	lea    r10d,[r14]
  2a:	45 8d 1e             	lea    r11d,[r14]
  2d:	45 8d 26             	lea    r12d,[r14]
  30:	41 8d 1e             	lea    ebx,[r14]
  33:	41 8d 16             	lea    edx,[r14]
  36:	45 8d 0e             	lea    r9d,[r14]
  39:	45 8d 16             	lea    r10d,[r14]
  3c:	45 8d 1e             	lea    r11d,[r14]
  3f:	45 8d 26             	lea    r12d,[r14]
  42:	41 8d 1e             	lea    ebx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 0e             	lea    r9d,[r14]
  4b:	45 8d 16             	lea    r10d,[r14]
  4e:	45 8d 1e             	lea    r11d,[r14]
  51:	45 8d 26             	lea    r12d,[r14]
  54:	49 d3 d0             	rcl    r8,cl

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 15.8
- Reference cycles: 14.17
- UOPS_PORT_5: 15.4
- UOPS_PORT_1: 14.6

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c0          	movq2dq xmm0,mm0
   4:	f3 0f d6 c8          	movq2dq xmm1,mm0
   8:	f3 0f d6 d0          	movq2dq xmm2,mm0
   c:	f3 0f d6 d8          	movq2dq xmm3,mm0
  10:	f3 0f d6 e0          	movq2dq xmm4,mm0
  14:	f3 0f d6 e8          	movq2dq xmm5,mm0
  18:	f3 0f d6 f0          	movq2dq xmm6,mm0
  1c:	f3 0f d6 f8          	movq2dq xmm7,mm0
  20:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  25:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  2a:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2f:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  34:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  39:	f3 0f d6 c0          	movq2dq xmm0,mm0
  3d:	f3 0f d6 c8          	movq2dq xmm1,mm0
  41:	f3 0f d6 d0          	movq2dq xmm2,mm0
  45:	f3 0f d6 d8          	movq2dq xmm3,mm0
  49:	f3 0f d6 e0          	movq2dq xmm4,mm0
  4d:	f3 0f d6 e8          	movq2dq xmm5,mm0
  51:	f3 0f d6 f0          	movq2dq xmm6,mm0
  55:	f3 0f d6 f8          	movq2dq xmm7,mm0
  59:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  5e:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  63:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  68:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  6d:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  72:	f3 0f d6 c0          	movq2dq xmm0,mm0
  76:	f3 0f d6 c8          	movq2dq xmm1,mm0
  7a:	f3 0f d6 d0          	movq2dq xmm2,mm0
  7e:	f3 0f d6 d8          	movq2dq xmm3,mm0
  82:	f3 0f d6 e0          	movq2dq xmm4,mm0
  86:	f3 0f d6 e8          	movq2dq xmm5,mm0
  8a:	f3 0f d6 f0          	movq2dq xmm6,mm0
  8e:	f3 0f d6 f8          	movq2dq xmm7,mm0
  92:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  97:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  9c:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  a1:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  a6:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  ab:	f3 0f d6 c0          	movq2dq xmm0,mm0
  af:	f3 0f d6 c8          	movq2dq xmm1,mm0
  b3:	f3 0f d6 d0          	movq2dq xmm2,mm0
  b7:	49 d3 d0             	rcl    r8,cl

Init:
```
VZEROALL;
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 43.0
- Core cycles: 16.22
- Reference cycles: 14.84
- UOPS_PORT_5: 14.91
- UOPS_PORT_1: 14.78
- UOPS_PORT_0: 14.61

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf ca          	movsx  r9d,r10w
   4:	45 0f bf da          	movsx  r11d,r10w
   8:	45 0f bf e2          	movsx  r12d,r10w
   c:	41 0f bf da          	movsx  ebx,r10w
  10:	41 0f bf d2          	movsx  edx,r10w
  14:	45 0f bf ca          	movsx  r9d,r10w
  18:	45 0f bf da          	movsx  r11d,r10w
  1c:	45 0f bf e2          	movsx  r12d,r10w
  20:	41 0f bf da          	movsx  ebx,r10w
  24:	41 0f bf d2          	movsx  edx,r10w
  28:	45 0f bf ca          	movsx  r9d,r10w
  2c:	45 0f bf da          	movsx  r11d,r10w
  30:	45 0f bf e2          	movsx  r12d,r10w
  34:	41 0f bf da          	movsx  ebx,r10w
  38:	41 0f bf d2          	movsx  edx,r10w
  3c:	45 0f bf ca          	movsx  r9d,r10w
  40:	45 0f bf da          	movsx  r11d,r10w
  44:	45 0f bf e2          	movsx  r12d,r10w
  48:	41 0f bf da          	movsx  ebx,r10w
  4c:	41 0f bf d2          	movsx  edx,r10w
  50:	45 0f bf ca          	movsx  r9d,r10w
  54:	45 0f bf da          	movsx  r11d,r10w
  58:	45 0f bf e2          	movsx  r12d,r10w
  5c:	41 0f bf da          	movsx  ebx,r10w
  60:	41 0f bf d2          	movsx  edx,r10w
  64:	45 0f bf ca          	movsx  r9d,r10w
  68:	45 0f bf da          	movsx  r11d,r10w
  6c:	45 0f bf e2          	movsx  r12d,r10w
  70:	41 0f bf da          	movsx  ebx,r10w
  74:	41 0f bf d2          	movsx  edx,r10w
  78:	45 0f bf ca          	movsx  r9d,r10w
  7c:	45 0f bf da          	movsx  r11d,r10w
  80:	45 0f bf e2          	movsx  r12d,r10w
  84:	41 0f bf da          	movsx  ebx,r10w
  88:	41 0f bf d2          	movsx  edx,r10w
  8c:	45 0f bf ca          	movsx  r9d,r10w
  90:	45 0f bf da          	movsx  r11d,r10w
  94:	45 0f bf e2          	movsx  r12d,r10w
  98:	41 0f bf da          	movsx  ebx,r10w
  9c:	41 0f bf d2          	movsx  edx,r10w
  a0:	45 0f bf ca          	movsx  r9d,r10w
  a4:	45 0f bf da          	movsx  r11d,r10w
  a8:	45 0f bf e2          	movsx  r12d,r10w
  ac:	41 0f bf da          	movsx  ebx,r10w
  b0:	41 0f bf d2          	movsx  edx,r10w
  b4:	45 0f bf ca          	movsx  r9d,r10w
  b8:	45 0f bf da          	movsx  r11d,r10w
  bc:	45 0f bf e2          	movsx  r12d,r10w
  c0:	41 0f bf da          	movsx  ebx,r10w
  c4:	41 0f bf d2          	movsx  edx,r10w
  c8:	45 0f bf ca          	movsx  r9d,r10w
  cc:	45 0f bf da          	movsx  r11d,r10w
  d0:	45 0f bf e2          	movsx  r12d,r10w
  d4:	41 0f bf da          	movsx  ebx,r10w
  d8:	41 0f bf d2          	movsx  edx,r10w
  dc:	45 0f bf ca          	movsx  r9d,r10w
  e0:	49 d3 d0             	rcl    r8,cl

Show nanoBench command
Results:
- Instructions retired: 57.0
- Core cycles: 19.18
- Reference cycles: 16.94
- UOPS_PORT_6: 17.29
- UOPS_PORT_5: 16.06
- UOPS_PORT_1: 15.0
- UOPS_PORT_0: 15.65

⇨ 2 μops that can only use ports {'0', '1', '5', '6'}