VPDPBUSD (ZMM, K, ZMM, ZMM)

Operands

• Operand 1 (r/w): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 2 (r): Register (K1, K2, K3, K4, K5, K6, K7)
• Operand 3 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 4 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 5
  • Latency operand 4 → 1: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 5
  • Latency operand 4 → 1: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 5
  • Latency operand 4 → 1: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 5
  • Latency operand 4 → 1: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0
• Documentation
• Throughput: 1.0

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 5
  • Latency operand 4 → 1: 5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p05

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 4
  • Latency operand 4 → 1: 4
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
• Port usage: 1*FP01