VPCLMULQDQ (YMM, YMM, YMM, I8)

Operands

• Operand 1 (w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 3 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 4 (r): 8-bit immediate

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• AMD Zen 4
• AMD Zen 3

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p5

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 5
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 8
  • Latency operand 3 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 8
  • Latency operand 3 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 8
  • Latency operand 3 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 4
• Throughput
  • Computed from the port usage: 0.75
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
• Port usage: 1*FP01+1*FP123+1*FP23

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 4
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
• Port usage: 1*FP0123+1*FP1+1*FP12