VPCLMULQDQ (YMM, YMM, YMM, I8)

Experiment 1

Instruction: VPCLMULQDQ YMM1, YMM0, YMM2, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e3 7d 44 ca 02    	vpclmullqhqdq ymm1,ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 6.24
- UOPS_EXECUTED.THREAD: 6.02

Experiment 2

Instruction: VPCLMULQDQ YMM1, YMM0, YMM2, 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 7d 44 ca 02    	vpclmullqhqdq ymm1,ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 5.97

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCLMULQDQ YMM1, YMM0, YMM2, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e3 7d 44 ca 02    	vpclmullqhqdq ymm1,ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPCLMULQDQ YMM0, YMM1, YMM2, 2;
VPCLMULQDQ YMM2, YMM0, YMM1, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 5.76
- UOPS_EXECUTED.THREAD: 5.99

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCLMULQDQ YMM1, YMM0, YMM2, 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 7d 44 ca 02    	vpclmullqhqdq ymm1,ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPCLMULQDQ YMM0, YMM1, YMM2, 2;
VPCLMULQDQ YMM2, YMM0, YMM1, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 5.92
- UOPS_EXECUTED.THREAD: 6.03

Experiment 1

Instruction: VPCLMULQDQ YMM1, YMM2, YMM0, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e3 6d 44 c8 02    	vpclmullqhqdq ymm1,ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.04
- Reference cycles: 5.76
- UOPS_EXECUTED.THREAD: 6.02

Experiment 2

Instruction: VPCLMULQDQ YMM1, YMM2, YMM0, 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 44 c8 02    	vpclmullqhqdq ymm1,ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 5.92
- UOPS_EXECUTED.THREAD: 5.96

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCLMULQDQ YMM1, YMM2, YMM0, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e3 6d 44 c8 02    	vpclmullqhqdq ymm1,ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPCLMULQDQ YMM2, YMM0, YMM1, 2;
VPCLMULQDQ YMM0, YMM1, YMM2, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 5.76
- UOPS_EXECUTED.THREAD: 6.01

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCLMULQDQ YMM1, YMM2, YMM0, 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 44 c8 02    	vpclmullqhqdq ymm1,ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPCLMULQDQ YMM2, YMM0, YMM1, 2;
VPCLMULQDQ YMM0, YMM1, YMM2, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 6.24
- UOPS_EXECUTED.THREAD: 5.99

VPCLMULQDQ (YMM, YMM, YMM, I8) - Latency

Operands

Latency operand 2 → 1: 3

Latency operand 3 → 1: 3

Latency operand 2 → 1: 3

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 3

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)