VMOVSD (XMM, M64)
Summary:
"Move or Merge Scalar Double-Precision Floating-Point Value"
Reference:
https://www.felixcloutier.com/x86/MOVSD.html
Extension:
AVX
Category:
DATAXFER
ISA-Set:
AVX
CPL:
3
iform:
VMOVSD_XMMdq_MEMq
iclass:
VMOVSD
ASM:
VMOVSD
Operands
Operand 1 (w): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
Operand 2 (r): Memory
Available performance data
Alder Lake-P
Alder Lake-E
Rocket Lake
Tiger Lake
Ice Lake
Cascade Lake
Cannon Lake
Skylake-X
Coffee Lake
Kaby Lake
Skylake
Broadwell
Haswell
Ivy Bridge
Sandy Bridge
AMD Zen 4
AMD Zen 3
AMD Zen 2
AMD Zen+
Alder Lake-P
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.33
Measured (loop):
0.33
Measured (unrolled):
0.33
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23A
Alder Lake-E
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤9
Latency operand 2 → 1 (address, index register):
≤9
Latency operand 2 → 1 (memory):
≤7
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Rocket Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Tiger Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Ice Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Documentation
Latency: 6.0
Throughput: 0.5
Cascade Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Cannon Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Skylake-X
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
IACA 3.0
Throughput
Computed from the port usage: 0.50
IACA:
0.49
Number of μops:
1
Port usage:
1*p23
Coffee Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Kaby Lake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
Skylake
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤7
Latency operand 2 → 1 (address, index register):
≤7
Latency operand 2 → 1 (memory):
≤4
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
IACA 3.0
Throughput
Computed from the port usage: 0.50
IACA:
0.49
Number of μops:
1
Port usage:
1*p23
Broadwell
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤6
Latency operand 2 → 1 (address, index register):
≤6
Latency operand 2 → 1 (memory):
≤5
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.2
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
IACA 3.0
Throughput
Computed from the port usage: 0.50
IACA:
0.49
Number of μops:
1
Port usage:
1*p23
Haswell
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤6
Latency operand 2 → 1 (address, index register):
≤6
Latency operand 2 → 1 (memory):
≤5
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.1
Latency:
6
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.2
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
IACA 3.0
Throughput
Computed from the port usage: 0.50
IACA:
0.49
Number of μops:
1
Port usage:
1*p23
Ivy Bridge
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤6
Latency operand 2 → 1 (address, index register):
≤6
Latency operand 2 → 1 (memory):
≤5
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.1
Latency:
6
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.2
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
Sandy Bridge
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤6
Latency operand 2 → 1 (address, index register):
≤6
Latency operand 2 → 1 (memory):
≤5
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Retire slots: 1
Decoded (MITE): 1
Microcode Sequencer (MS): 0
Port usage:
1*p23
IACA 2.1
Latency:
6
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.2
Throughput
Computed from the port usage: 0.50
IACA:
0.50 (with the -no_interiteration flag: 0.50)
Number of μops:
1
Port usage:
1*p23
IACA 2.3
Throughput
Computed from the port usage: 0.50
IACA:
0.50
Number of μops:
1
Port usage:
1*p23
AMD Zen 4
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤8
Latency operand 2 → 1 (address, index register):
≤8
Latency operand 2 → 1 (memory):
≤8
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
AMD Zen 3
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤8
Latency operand 2 → 1 (address, index register):
≤8
Latency operand 2 → 1 (memory):
≤8
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
AMD Zen 2
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤8
Latency operand 2 → 1 (address, index register):
≤8
Latency operand 2 → 1 (memory):
≤7
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
AMD Zen+
Measurements
Latencies
Latency operand 2 → 1 (address, base register):
≤8
Latency operand 2 → 1 (address, index register):
≤8
Latency operand 2 → 1 (memory):
≤7
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1