VMOVSD (XMM, M64)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.39
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.47
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.78
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 1.81
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.63
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]
  2f:	c4 41 7b 10 46 40    	vmovsd xmm8,QWORD PTR [r14+0x40]
  35:	c4 41 7b 10 4e 48    	vmovsd xmm9,QWORD PTR [r14+0x48]
  3b:	c4 41 7b 10 56 50    	vmovsd xmm10,QWORD PTR [r14+0x50]
  41:	c4 41 7b 10 5e 58    	vmovsd xmm11,QWORD PTR [r14+0x58]
  47:	c4 41 7b 10 66 60    	vmovsd xmm12,QWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.51
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]
  2f:	c4 41 7b 10 46 40    	vmovsd xmm8,QWORD PTR [r14+0x40]
  35:	c4 41 7b 10 4e 48    	vmovsd xmm9,QWORD PTR [r14+0x48]
  3b:	c4 41 7b 10 56 50    	vmovsd xmm10,QWORD PTR [r14+0x50]
  41:	c4 41 7b 10 5e 58    	vmovsd xmm11,QWORD PTR [r14+0x58]
  47:	c4 41 7b 10 66 60    	vmovsd xmm12,QWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 6.52
- Reference cycles: 6.01
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7b 10 06       	vmovsd xmm0,QWORD PTR [r14]
   5:	c4 c1 7b 10 4e 08    	vmovsd xmm1,QWORD PTR [r14+0x8]
   b:	c4 c1 7b 10 56 10    	vmovsd xmm2,QWORD PTR [r14+0x10]
  11:	c4 c1 7b 10 5e 18    	vmovsd xmm3,QWORD PTR [r14+0x18]
  17:	c4 c1 7b 10 66 20    	vmovsd xmm4,QWORD PTR [r14+0x20]
  1d:	c4 c1 7b 10 6e 28    	vmovsd xmm5,QWORD PTR [r14+0x28]
  23:	c4 c1 7b 10 76 30    	vmovsd xmm6,QWORD PTR [r14+0x30]
  29:	c4 c1 7b 10 7e 38    	vmovsd xmm7,QWORD PTR [r14+0x38]
  2f:	c4 41 7b 10 46 40    	vmovsd xmm8,QWORD PTR [r14+0x40]
  35:	c4 41 7b 10 4e 48    	vmovsd xmm9,QWORD PTR [r14+0x48]
  3b:	c4 41 7b 10 56 50    	vmovsd xmm10,QWORD PTR [r14+0x50]
  41:	c4 41 7b 10 5e 58    	vmovsd xmm11,QWORD PTR [r14+0x58]
  47:	c4 41 7b 10 66 60    	vmovsd xmm12,QWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.52
- Reference cycles: 5.99
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.34
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.47
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.35

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.47
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.83
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 1.86
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.11

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.09
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.08

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.72
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	c4 01 7b 10 44 2e 40 	vmovsd xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	c4 01 7b 10 4c 2e 48 	vmovsd xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	c4 01 7b 10 54 2e 50 	vmovsd xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	c4 01 7b 10 5c 2e 58 	vmovsd xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	c4 01 7b 10 64 2e 60 	vmovsd xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.51
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	c4 01 7b 10 44 2e 40 	vmovsd xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	c4 01 7b 10 4c 2e 48 	vmovsd xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	c4 01 7b 10 54 2e 50 	vmovsd xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	c4 01 7b 10 5c 2e 58 	vmovsd xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	c4 01 7b 10 64 2e 60 	vmovsd xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 6.52
- Reference cycles: 5.86
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7b 10 04 2e    	vmovsd xmm0,QWORD PTR [r14+r13*1]
   6:	c4 81 7b 10 4c 2e 08 	vmovsd xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	c4 81 7b 10 54 2e 10 	vmovsd xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	c4 81 7b 10 5c 2e 18 	vmovsd xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 81 7b 10 64 2e 20 	vmovsd xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	c4 81 7b 10 6c 2e 28 	vmovsd xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	c4 81 7b 10 74 2e 30 	vmovsd xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	c4 81 7b 10 7c 2e 38 	vmovsd xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	c4 01 7b 10 44 2e 40 	vmovsd xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	c4 01 7b 10 4c 2e 48 	vmovsd xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	c4 01 7b 10 54 2e 50 	vmovsd xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	c4 01 7b 10 5c 2e 58 	vmovsd xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	c4 01 7b 10 64 2e 60 	vmovsd xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.52
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 6.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

VMOVSD (XMM, M64) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10