VMOVNTDQA (ZMM, M512)

Operands

• Operand 1 (w): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 2 (r): Memory

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.33
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Retire slots: 1
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p23A

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.62
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23
• Documentation
• Latency: 7.0
• Throughput: 0.5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 1
• Port usage: 1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.49
• Number of μops: 1
• Port usage: 1*p23

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤9
  • Latency operand 2 → 1 (address, index register): ≤9
  • Latency operand 2 → 1 (memory): ≤11
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1