VMOVNTDQA (ZMM, M512)

With unroll_count=500 and no inner loop

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.27
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.48
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.02
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.14
- Reference cycles: 2.04
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 8.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.79
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.25
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 17.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.08
- Reference cycles: 4.21
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.03
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 7d 48 2a 46 08 	vmovntdqa zmm8,ZMMWORD PTR [r14+0x200]
  3e:	62 52 7d 48 2a 4e 09 	vmovntdqa zmm9,ZMMWORD PTR [r14+0x240]
  45:	62 52 7d 48 2a 56 0a 	vmovntdqa zmm10,ZMMWORD PTR [r14+0x280]
  4c:	62 52 7d 48 2a 5e 0b 	vmovntdqa zmm11,ZMMWORD PTR [r14+0x2c0]
  53:	62 52 7d 48 2a 66 0c 	vmovntdqa zmm12,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 7d 48 2a 46 0d 	vmovntdqa zmm16,ZMMWORD PTR [r14+0x340]
  61:	62 c2 7d 48 2a 4e 0e 	vmovntdqa zmm17,ZMMWORD PTR [r14+0x380]
  68:	62 c2 7d 48 2a 56 0f 	vmovntdqa zmm18,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 17.28
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 7d 48 2a 46 08 	vmovntdqa zmm8,ZMMWORD PTR [r14+0x200]
  3e:	62 52 7d 48 2a 4e 09 	vmovntdqa zmm9,ZMMWORD PTR [r14+0x240]
  45:	62 52 7d 48 2a 56 0a 	vmovntdqa zmm10,ZMMWORD PTR [r14+0x280]
  4c:	62 52 7d 48 2a 5e 0b 	vmovntdqa zmm11,ZMMWORD PTR [r14+0x2c0]
  53:	62 52 7d 48 2a 66 0c 	vmovntdqa zmm12,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 7d 48 2a 46 0d 	vmovntdqa zmm16,ZMMWORD PTR [r14+0x340]
  61:	62 c2 7d 48 2a 4e 0e 	vmovntdqa zmm17,ZMMWORD PTR [r14+0x380]
  68:	62 c2 7d 48 2a 56 0f 	vmovntdqa zmm18,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.27
- Reference cycles: 8.3
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.76
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.25
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 7d 48 2a 06    	vmovntdqa zmm0,ZMMWORD PTR [r14]
   6:	62 d2 7d 48 2a 4e 01 	vmovntdqa zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 7d 48 2a 56 02 	vmovntdqa zmm2,ZMMWORD PTR [r14+0x80]
  14:	62 d2 7d 48 2a 5e 03 	vmovntdqa zmm3,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 7d 48 2a 66 04 	vmovntdqa zmm4,ZMMWORD PTR [r14+0x100]
  22:	62 d2 7d 48 2a 6e 05 	vmovntdqa zmm5,ZMMWORD PTR [r14+0x140]
  29:	62 d2 7d 48 2a 76 06 	vmovntdqa zmm6,ZMMWORD PTR [r14+0x180]
  30:	62 d2 7d 48 2a 7e 07 	vmovntdqa zmm7,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 7d 48 2a 46 08 	vmovntdqa zmm8,ZMMWORD PTR [r14+0x200]
  3e:	62 52 7d 48 2a 4e 09 	vmovntdqa zmm9,ZMMWORD PTR [r14+0x240]
  45:	62 52 7d 48 2a 56 0a 	vmovntdqa zmm10,ZMMWORD PTR [r14+0x280]
  4c:	62 52 7d 48 2a 5e 0b 	vmovntdqa zmm11,ZMMWORD PTR [r14+0x2c0]
  53:	62 52 7d 48 2a 66 0c 	vmovntdqa zmm12,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 7d 48 2a 46 0d 	vmovntdqa zmm16,ZMMWORD PTR [r14+0x340]
  61:	62 c2 7d 48 2a 4e 0e 	vmovntdqa zmm17,ZMMWORD PTR [r14+0x380]
  68:	62 c2 7d 48 2a 56 0f 	vmovntdqa zmm18,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.11
- Reference cycles: 8.15
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.02
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.92
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.73
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 2.09
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.53
- Reference cycles: 0.51
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.48
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.52
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.19
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.26
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.78
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 8.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 8.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.06
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.03
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 17.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.07
- Reference cycles: 3.82
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.03
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 7d 48 2a 44 2e 	vmovntdqa zmm8,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 7d 48 2a 4c 2e 	vmovntdqa zmm9,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 7d 48 2a 54 2e 	vmovntdqa zmm10,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 7d 48 2a 5c 2e 	vmovntdqa zmm11,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 12 7d 48 2a 64 2e 	vmovntdqa zmm12,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 7d 48 2a 44 2e 	vmovntdqa zmm16,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 7d 48 2a 4c 2e 	vmovntdqa zmm17,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 7d 48 2a 54 2e 	vmovntdqa zmm18,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.06
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 7d 48 2a 44 2e 	vmovntdqa zmm8,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 7d 48 2a 4c 2e 	vmovntdqa zmm9,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 7d 48 2a 54 2e 	vmovntdqa zmm10,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 7d 48 2a 5c 2e 	vmovntdqa zmm11,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 12 7d 48 2a 64 2e 	vmovntdqa zmm12,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 7d 48 2a 44 2e 	vmovntdqa zmm16,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 7d 48 2a 4c 2e 	vmovntdqa zmm17,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 7d 48 2a 54 2e 	vmovntdqa zmm18,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 12.02
- Reference cycles: 11.39
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 15.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 7d 48 2a 04 2e 	vmovntdqa zmm0,ZMMWORD PTR [r14+r13*1]
   7:	62 92 7d 48 2a 4c 2e 	vmovntdqa zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 7d 48 2a 54 2e 	vmovntdqa zmm2,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 7d 48 2a 5c 2e 	vmovntdqa zmm3,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 7d 48 2a 64 2e 	vmovntdqa zmm4,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 7d 48 2a 6c 2e 	vmovntdqa zmm5,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 7d 48 2a 74 2e 	vmovntdqa zmm6,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 92 7d 48 2a 7c 2e 	vmovntdqa zmm7,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 7d 48 2a 44 2e 	vmovntdqa zmm8,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 7d 48 2a 4c 2e 	vmovntdqa zmm9,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 7d 48 2a 54 2e 	vmovntdqa zmm10,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 7d 48 2a 5c 2e 	vmovntdqa zmm11,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 12 7d 48 2a 64 2e 	vmovntdqa zmm12,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 7d 48 2a 44 2e 	vmovntdqa zmm16,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 7d 48 2a 4c 2e 	vmovntdqa zmm17,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 7d 48 2a 54 2e 	vmovntdqa zmm18,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.11
- Reference cycles: 7.71
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.02
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VMOVNTDQA (ZMM, M512) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10