VMASKMOVPD (M256, YMM, YMM)

Operands

• Operand 1 (w): Memory
• Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 3 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p49+1*p78

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤20
  • Latency operand 1 → 1 (address, index register): ≤20
  • Latency operand 2 → 1: ≤18
  • Latency operand 3 → 1: ≤17
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p49+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p49+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p0+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.85
• Number of μops: 2
• Port usage: 1*p0+1*p237+1*p4

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 2 → 1: ≤14
  • Latency operand 3 → 1: ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p0+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.85
• Number of μops: 2
• Port usage: 1*p0+1*p237+1*p4

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.92
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.92
• Number of μops: 4
• Port usage: 1*p0+1*p15+1*p237+1*p4

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 2.00)
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 2.00)
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 2.00)
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00 (with the -no_interiteration flag: 2.00)
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 3
• Port usage: 1*p01+1*p23+2*p4

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 3.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 18
• Port usage: 3*FP1+5*FP45

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤3
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Computed from the port usage: 3.00
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 18
• Port usage: 3*FP1+5*FP45

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 19

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤3
  • Latency operand 1 → 1 (address, index register): ≤3
  • Latency operand 2 → 1: ≤0
  • Latency operand 3 → 1: ≤0
• Throughput
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 18