VGATHERQPD (ZMM, K, VSIB_ZMM)

Operands

• Operand 1 (r/w): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 2 (r/w): Register (K1, K2, K3, K4, K5, K6, K7)
• Operand 3 (r): Memory

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 2
  • Latency operand 2 → 1: 23
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1 (address, base register): ≤25
  • Latency operand 3 → 1 (address, index register): ≤28
  • Latency operand 3 → 1 (memory): ≤22
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 6
  • Retire slots: 5
  • Decoded (MITE): 5
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23A+2*p5

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 2: 4
  • Latency operand 2 → 1: 21
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1 (address, base register): ≤18
  • Latency operand 3 → 1 (address, index register): ≤21
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 4
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+8*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 4.00
  • IACA: 5.21
• Number of μops: 5
• Port usage: 1*p0+1*p0156+1*p05+8*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 4.00
  • IACA: 3.99
• Number of μops: 5
• Port usage: 1*p0+1*p0156+1*p05+8*p23

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1: 12
  • Latency operand 1 → 2: 11
  • Latency operand 2 → 1: 19
  • Latency operand 2 → 2: 5
  • Latency operand 3 → 1 (address, base register): ≤24
  • Latency operand 3 → 1 (address, index register): ≤26
  • Latency operand 3 → 1 (memory): ≤16
• Throughput
  • Computed from the port usage: 5.00
  • Measured (loop): 9.02
  • Measured (unrolled): 8.95
• Number of μops
  • Executed: 48
• Port usage: 5*FP0123+3*FP12+5*FP123+1*FP23+10*FP45