VAESENC (XMM, XMM, M128)

Operands

• Operand 1 (w): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
• Operand 2 (r): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
• Operand 3 (r): Memory

Available performance data

• Arrow Lake-P
• Arrow Lake-E
• Meteor Lake-P
• Meteor Lake-E
• Emerald Rapids
• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• AMD Zen 5
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Arrow Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (6 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*LD+1*UNKNOWN

Arrow Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤14
  • Latency operand 3 → 1 (address, index register): ≤14
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Meteor Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23A

Meteor Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤14
  • Latency operand 3 → 1 (address, index register): ≤14
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Emerald Rapids

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23A

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤14
  • Latency operand 3 → 1 (address, index register): ≤14
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23
• Documentation
• Throughput: 0.5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.53
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p01+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 2 → 1: 7
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤13
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

Haswell

• Measurements
• Latencies
  • Latency operand 2 → 1: 7
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤13
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.1
• Latency: 13
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 2 → 1: 8
  • Latency operand 3 → 1 (address, base register): ≤7
  • Latency operand 3 → 1 (address, index register): ≤7
  • Latency operand 3 → 1 (memory): ≤6
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.16
  • Measured (unrolled): 1.33
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.1
• Latency: 13
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 2 → 1: 8
  • Latency operand 3 → 1 (address, base register): ≤7
  • Latency operand 3 → 1 (address, index register): ≤7
  • Latency operand 3 → 1 (memory): ≤6
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.20
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.1
• Latency: 13
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p015+1*p23+1*p5

AMD Zen 5

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01
• Documentation
• Latency: 4
• Throughput: 0.50
• Number of μops: 1
• Port usage: FP0/1

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01
• Documentation
• Latency: 4
• Throughput: 0.50
• Number of μops: 1
• Port usage: FP0/1

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01
• Documentation
• Latency: 4
• Throughput: 0.50
• Number of μops: 1
• Port usage: FP0/1

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01

AMD Zen+

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01