VAESENC (XMM, XMM, M128)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.01
- UOPS_PORT_3: 2.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.6
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 7.15
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 42 71 dc 8e 80 00 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 42 71 dc 96 90 00 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 42 71 dc 9e a0 00 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 42 71 dc a6 b0 00 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.0
- Reference cycles: 10.46
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 42 71 dc 8e 80 00 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 42 71 dc 96 90 00 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 42 71 dc 9e a0 00 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 42 71 dc a6 b0 00 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.02
- Reference cycles: 10.8
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c2 71 dc 06       	vaesenc xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c2 71 dc 56 10    	vaesenc xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c2 71 dc 5e 20    	vaesenc xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c2 71 dc 66 30    	vaesenc xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c2 71 dc 6e 40    	vaesenc xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c2 71 dc 76 50    	vaesenc xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c2 71 dc 7e 60    	vaesenc xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 42 71 dc 46 70    	vaesenc xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 42 71 dc 8e 80 00 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 42 71 dc 96 90 00 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 42 71 dc 9e a0 00 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 42 71 dc a6 b0 00 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.02
- Reference cycles: 10.8
- UOPS_EXECUTED.THREAD: 24.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 1.92
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.91

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.6
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 7.23
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 17.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 7.15
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 02 71 dc 8c 2e 80 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 02 71 dc 94 2e 90 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 02 71 dc 9c 2e a0 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 02 71 dc a4 2e b0 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.0
- Reference cycles: 10.71
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 02 71 dc 8c 2e 80 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 02 71 dc 94 2e 90 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 02 71 dc 9c 2e a0 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 02 71 dc a4 2e b0 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.02
- Reference cycles: 10.8
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 7.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.02

With loop_count=100 and unroll_count=10

Code:

   0:	c4 82 71 dc 04 2e    	vaesenc xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 82 71 dc 54 2e 10 	vaesenc xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 82 71 dc 5c 2e 20 	vaesenc xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 82 71 dc 64 2e 30 	vaesenc xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 82 71 dc 6c 2e 40 	vaesenc xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 82 71 dc 74 2e 50 	vaesenc xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 82 71 dc 7c 2e 60 	vaesenc xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 02 71 dc 44 2e 70 	vaesenc xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 02 71 dc 8c 2e 80 	vaesenc xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 02 71 dc 94 2e 90 	vaesenc xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 02 71 dc 9c 2e a0 	vaesenc xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 02 71 dc a4 2e b0 	vaesenc xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.02
- Reference cycles: 10.8
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

VAESENC (XMM, XMM, M128) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10