MOVBE (R32, M32)

Operands

• Operand 1 (w): Register (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D)
• Operand 2 (r): Memory

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤1
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23
• Documentation
• Latency: 6.0
• Throughput: 0.5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23

Haswell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p15+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p15+1*p23

Tremont

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 4
  • Latency operand 2 → 1 (address, index register): 4
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 4
  • Latency operand 2 → 1 (address, index register): 4
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Goldmont

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 4
  • Latency operand 2 → 1 (address, index register): 4
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Airmont

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 4
  • Latency operand 2 → 1 (address, index register): 4
  • Latency operand 2 → 1 (memory): ≤7
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Bonnell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 4
  • Latency operand 2 → 1 (address, index register): 4
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤7
• Throughput
  • Measured (loop): 0.33
  • Measured (unrolled): 0.33 (if an indexed addressing mode is used: 0.37)
• Number of μops
  • Executed: 1 (if an indexed addressing mode is used: 2)

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤6
• Throughput
  • Measured (loop): 0.33
  • Measured (unrolled): 0.33
• Number of μops
  • Executed: 1
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU

AMD Zen+

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤7
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU