MOVBE (R32, M32)

With unroll_count=500 and no inner loop

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.98
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.58
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.42
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.93
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.58
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.42
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.93
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.06
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.46
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.54
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.73
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.67
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.53
- Reference cycles: 0.47
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=100

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.66
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.34
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.67
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.14
- Reference cycles: 1.87
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 8.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.99
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]
  17:	45 0f 38 f0 66 10    	movbe  r12d,DWORD PTR [r14+0x10]
  1d:	41 0f 38 f0 5e 14    	movbe  ebx,DWORD PTR [r14+0x14]
  23:	41 0f 38 f0 4e 18    	movbe  ecx,DWORD PTR [r14+0x18]
  29:	41 0f 38 f0 56 1c    	movbe  edx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.09
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.67
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]
  17:	45 0f 38 f0 66 10    	movbe  r12d,DWORD PTR [r14+0x10]
  1d:	41 0f 38 f0 5e 14    	movbe  ebx,DWORD PTR [r14+0x14]
  23:	41 0f 38 f0 4e 18    	movbe  ecx,DWORD PTR [r14+0x18]
  29:	41 0f 38 f0 56 1c    	movbe  edx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.27
- Reference cycles: 3.72
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	45 0f 38 f0 06       	movbe  r8d,DWORD PTR [r14]
   5:	45 0f 38 f0 4e 04    	movbe  r9d,DWORD PTR [r14+0x4]
   b:	45 0f 38 f0 56 08    	movbe  r10d,DWORD PTR [r14+0x8]
  11:	45 0f 38 f0 5e 0c    	movbe  r11d,DWORD PTR [r14+0xc]
  17:	45 0f 38 f0 66 10    	movbe  r12d,DWORD PTR [r14+0x10]
  1d:	41 0f 38 f0 5e 14    	movbe  ebx,DWORD PTR [r14+0x14]
  23:	41 0f 38 f0 4e 18    	movbe  ecx,DWORD PTR [r14+0x18]
  29:	41 0f 38 f0 56 1c    	movbe  edx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.08
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 3.98
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.02
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.89
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.58
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.42
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.58
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.42
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.98
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.06
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.46
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.54
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.67
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.89
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.58
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.42
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.66
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.34
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.67
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.14
- Reference cycles: 1.91
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 1.81
- UOPS_EXECUTED.THREAD: 8.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.99
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	47 0f 38 f0 64 2e 10 	movbe  r12d,DWORD PTR [r14+r13*1+0x10]
  22:	43 0f 38 f0 5c 2e 14 	movbe  ebx,DWORD PTR [r14+r13*1+0x14]
  29:	43 0f 38 f0 4c 2e 18 	movbe  ecx,DWORD PTR [r14+r13*1+0x18]
  30:	43 0f 38 f0 54 2e 1c 	movbe  edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.65
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.67
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	47 0f 38 f0 64 2e 10 	movbe  r12d,DWORD PTR [r14+r13*1+0x10]
  22:	43 0f 38 f0 5c 2e 14 	movbe  ebx,DWORD PTR [r14+r13*1+0x14]
  29:	43 0f 38 f0 4c 2e 18 	movbe  ecx,DWORD PTR [r14+r13*1+0x18]
  30:	43 0f 38 f0 54 2e 1c 	movbe  edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 7.12
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 17.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.67
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.33
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	47 0f 38 f0 04 2e    	movbe  r8d,DWORD PTR [r14+r13*1]
   6:	47 0f 38 f0 4c 2e 04 	movbe  r9d,DWORD PTR [r14+r13*1+0x4]
   d:	47 0f 38 f0 54 2e 08 	movbe  r10d,DWORD PTR [r14+r13*1+0x8]
  14:	47 0f 38 f0 5c 2e 0c 	movbe  r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	47 0f 38 f0 64 2e 10 	movbe  r12d,DWORD PTR [r14+r13*1+0x10]
  22:	43 0f 38 f0 5c 2e 14 	movbe  ebx,DWORD PTR [r14+r13*1+0x14]
  29:	43 0f 38 f0 4c 2e 18 	movbe  ecx,DWORD PTR [r14+r13*1+0x18]
  30:	43 0f 38 f0 54 2e 1c 	movbe  edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.08
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 3.98
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.02
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

MOVBE (R32, M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10