BTS (M64, 0)

Operands

• Operand 1 (r/w): Memory
• Operand 2 (r): 8-bit immediate
• Operand 3 (w, suppressed): Flags (AF: undef, CF: w, OF: undef, PF: undef, SF: undef)

Available performance data

• Arrow Lake-P
• Arrow Lake-E
• Meteor Lake-P
• Meteor Lake-E
• Emerald Rapids
• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 5
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Arrow Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 1
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.95
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (5 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*ALU+1*LD+1*STA+1*STD

Arrow Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤5
  • Latency operand 1 → 1 (address, index register): ≤5
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 0
  • Latency operand 1 → 3 (address, index register): 0
  • Latency operand 1 → 3 (memory): ≤2
• Throughput
  • Measured (loop): 0.55
  • Measured (unrolled): 0.58
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Meteor Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 1
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤1
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 0.98 (if an indexed addressing mode is used: 1.00)
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23A+1*p49+1*p78 (if an indexed addressing mode is used: 1*p01+1*p1+1*p15+1*p15B+1*p23A+1*p49+1*p78)

Meteor Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤3
  • Latency operand 1 → 1 (address, index register): ≤3
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 0
  • Latency operand 1 → 3 (address, index register): 0
  • Latency operand 1 → 3 (memory): ≤2
• Throughput
  • Measured (loop): 0.63
  • Measured (unrolled): 0.64
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Emerald Rapids

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 1
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤1
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23A+1*p49+1*p78 (if an indexed addressing mode is used: 1*p01+1*p1+1*p15+1*p15B+1*p23A+1*p49+1*p78)

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 1
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤1
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23A+1*p49+1*p78 (if an indexed addressing mode is used: 1*p01+1*p1+1*p15+1*p15B+1*p23A+1*p49+1*p78)

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤2
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 0
  • Latency operand 1 → 3 (address, index register): 0
  • Latency operand 1 → 3 (memory): ≤2
• Throughput
  • Measured (loop): 0.62
  • Measured (unrolled): 0.62
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 3 (address, base register): 2
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤2
• Throughput
  • Computed from the port usage: 0.50 (if an indexed addressing mode is used: 1.00)
  • Measured (loop): 0.60
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p49+1*p78 (if an indexed addressing mode is used: 1*p01+1*p05+1*p06+1*p23+2*p49+1*p78)

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤6
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.60
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤6
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.60
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p49+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p06+2*p23+1*p4)
• IACA 2.1
• Latency: 7
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p06+1*p23+1*p237+1*p4

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.1
• Latency: 7
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.02)
  • Measured (unrolled): 1.05 (if an indexed addressing mode is used: 1.06)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.1
• Latency: 7
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p05+2*p23+1*p4

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p05+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 6
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+1*p2+1*p3+1*p4

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p05+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 6
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p05+1*p2+1*p3+1*p4

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
• Port usage: 1*p015+1*p2+1*p3+1*p4

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
• Port usage: 1*p015+1*p2+1*p3+1*p4

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤6
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 5
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤6
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 5
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤7
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤5
• Throughput
  • Measured (loop): 1.03
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤5
  • Latency operand 1 → 1 (address, index register): ≤5
  • Latency operand 1 → 1 (memory): 2
  • Latency operand 1 → 3 (address, base register): 5
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤1
• Throughput
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

AMD Zen 5

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤17
  • Latency operand 1 → 1 (address, index register): ≤17
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 12
  • Latency operand 1 → 3 (address, index register): 12
  • Latency operand 1 → 3 (memory): ≤8
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
• Documentation
• Latency: NA
• Throughput: NA
• Number of μops: ucode
• Port usage: ucode

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 12
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤9
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 12
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤7
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 1 → 1 (address, index register): ≤16
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 10
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤8
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 10
  • Latency operand 1 → 3 (address, index register): 5
  • Latency operand 1 → 3 (memory): ≤7
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4