BTS (M64, 0)

Experiment 1

Instruction: BTS qword ptr [R14], 0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥8

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 6.89
- Reference cycles: 2.95
- UOPS_EXECUTED.THREAD: 13.0

Experiment 2 (with additional nop)

Instruction: BTS qword ptr [R14], 0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥8

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 7.13
- Reference cycles: 3.12
- UOPS_EXECUTED.THREAD: 13.0

Latency operand 1 → 1 (address, index register): ≤11

Experiment 1

Instruction: BTS qword ptr [R14+R13], 0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥8

Code:

   0:	4b 0f ba 2c 2e 00    	bts    QWORD PTR [r14+r13*1],0x0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 31 e5             	xor    r13,r12
  1f:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 19.06
- Reference cycles: 10.4
- UOPS_EXECUTED.THREAD: 13.0

Experiment 2 (with additional nop)

Instruction: BTS qword ptr [R14+R13], 0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥8

Code:

   0:	4b 0f ba 2c 2e 00    	bts    QWORD PTR [r14+r13*1],0x0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 31 e5             	xor    r13,r12
  1f:	4d 31 e5             	xor    r13,r12
  22:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 19.07
- Reference cycles: 10.4
- UOPS_EXECUTED.THREAD: 13.0

Latency operand 1 → 1 (memory): 1

Experiment 1

Instruction: BTS qword ptr [R14], 0

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.09
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 4.0

Experiment 2

Instruction: BTS qword ptr [R14], 0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12
Chain latency: 10

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 11.13
- Reference cycles: 6.24
- UOPS_EXECUTED.THREAD: 17.0

Latency operand 1 → 3 (address, base register): 2

Experiment 1

Instruction: BTS qword ptr [R14], 0
Chain instruction: CMOVC R14, R14
Chain latency: 1

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 5.0

Experiment 2 (with dependency-breaking instructions)

Instruction: BTS qword ptr [R14], 0
Chain instructions: CMOVC R14, R14;MOV qword ptr [R14], 0
Chain latency: 1

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 0f 42 f6          	cmovb  r14,r14
   9:	49 c7 06 00 00 00 00 	mov    QWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.0
- Reference cycles: 6.24
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 1 → 3 (address, index register): 6

Experiment 1

Instruction: BTS qword ptr [R14+R13], 0
Chain instruction: CMOVC R13, R13
Chain latency: 1

Code:

   0:	4b 0f ba 2c 2e 00    	bts    QWORD PTR [r14+r13*1],0x0
   6:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 3.99
- UOPS_EXECUTED.THREAD: 5.0

Experiment 2 (with dependency-breaking instructions)

Instruction: BTS qword ptr [R14+R13], 0
Chain instructions: CMOVC R13, R13;MOV qword ptr [R14], 0
Chain latency: 1

Code:

   0:	4b 0f ba 2c 2e 00    	bts    QWORD PTR [r14+r13*1],0x0
   6:	4d 0f 42 ed          	cmovb  r13,r13
   a:	49 c7 06 00 00 00 00 	mov    QWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 3.29
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 1 → 3 (memory): ≤2

Experiment 1

Instruction: BTS qword ptr [R14], 0
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥7

Code:

   0:	49 0f ba 2e 00       	bts    QWORD PTR [r14],0x0
   5:	4d 0f 42 e4          	cmovb  r12,r12
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 9.13
- Reference cycles: 4.68
- UOPS_EXECUTED.THREAD: 13.0

BTS (M64, 0) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤0

Latency operand 1 → 1 (address, index register): ≤11

Latency operand 1 → 1 (memory): 1

Latency operand 1 → 3 (address, base register): 2

Latency operand 1 → 3 (address, index register): 6

Latency operand 1 → 3 (memory): ≤2

Latency operand 1 → 1 (address, base register): ≤0

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤11

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 1

Experiment 1

Experiment 2

Latency operand 1 → 3 (address, base register): 2

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Latency operand 1 → 3 (address, index register): 6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Latency operand 1 → 3 (memory): ≤2

Experiment 1