On this page, we provide details on the caches of some of the processors that we analyzed. In particular, we provide information on the cache replacement policies, which are undocumented in the official manuals.

The results were obtained using the nanoBench Cache Analyzer, which is available on GitHub. The repository also contains a simulator for all the policies described on this page. Further information on the policies can be found in our paper nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems and in Andreas Abel's PhD thesis Automatic Generation of Models of Microarchitectures.

We provide results for the following processors:

Here, we provide a set of graphs for all CPUs showing the latencies when accessing memory areas of different sizes.