Papers

You can find more information on how the data on uops.info was obtained in the following papers.

If you would like to refer to uops.info, please cite the following paper, which describes the algorithms and their implementation underlying this site:

A. Abel and J. Reineke. uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures. ASPLOS.

@inproceedings{Abel19a,
  title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures},
  acmid = {3304062},
  address = {New York, NY, USA},
  author = {Abel, Andreas and Reineke, Jan},
  booktitle = {ASPLOS},
  doi = {10.1145/3297858.3304062},
  isbn = {978-1-4503-6240-5},
  location = {Providence, RI, USA},
  numpages = {14},
  pages = {673--686},
  publisher = {ACM},
  series = {ASPLOS '19},
  year = {2019},
  url = {http://doi.acm.org/10.1145/3297858.3304062}
}
OPEN PAPER

The following paper describes nanoBench, a tool for running microbenchmarks, which serves as the measurement infrastructure underlying uops.info. The paper also shows how to apply nanoBench to obtain highly detailed cache models:

A. Abel and J. Reineke. nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems. ISPASS.

@inproceedings{Abel20,
  title = {nanoBench: {A} Low-Overhead Tool for Running Microbenchmarks on x86 Systems},
  author = {Abel, Andreas and Reineke, Jan},
  booktitle = {2020 {IEEE} International Symposium on Performance Analysis of Systems and Software (ISPASS)},
  month = aug,
  year = {2020},
  url = {http://arxiv.org/abs/1911.03282}
}
OPEN PAPER

The following paper describes uiCA, a CPU simulator for predicting the throughput of basic blocks:

A. Abel and J. Reineke. uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures.

@inproceedings{Abel22,
  title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
  author = {Abel, Andreas and Reineke, Jan},
  booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
  series = {ICS '22},
  editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
  pages = {1--12},
  publisher = {{ACM}},
  month = {June},
  year = {2022},
  url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
}
OPEN PAPER

FACILE is an analytical throughput model that is fast, accurate, and interpretable:

A. Abel, S. Sharma, and J. Reineke. FACILE: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction.

@inproceedings{Abel23,
  title = {{FACILE}: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction},
  author = {Abel, Andreas and Sharma, Shrey and Reineke, Jan},
  booktitle = {{IEEE} International Symposium on Workload Characterization, {IISWC} 2023, Ghent, Belgium, October 1-3, 2023},
  publisher = {{IEEE}},
  pages = {87-99},
  year = {2023},
  doi = {10.1109/IISWC59245.2023.00023},
  url = {https://arxiv.org/pdf/2310.13212}
}
OPEN PAPER

Dissertation

Further information can also be found in Andreas Abel's PhD thesis "Automatic Generation of Models of Microarchitectures."

@phdthesis{Abel20b,
  author = {Andreas Abel},
  title = {Automatic Generation of Models of Microarchitectures},
  school = {Universit\"at des Saarlandes},
  month = jun,
  year = {2020},
  url = {https://d-nb.info/1212853466/34}
}

OPEN DISSERTATION