VPSLLVQ (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.29
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.3
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.3
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.28
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.2
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 1.19
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 2.37
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 2.4
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2
  28:	c4 62 f5 47 d2       	vpsllvq ymm10,ymm1,ymm2
  2d:	c4 62 f5 47 da       	vpsllvq ymm11,ymm1,ymm2
  32:	c4 62 f5 47 e2       	vpsllvq ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.5
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 11.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 11.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.5
- UOPS_PORT_1: 5.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.75

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2
  28:	c4 62 f5 47 d2       	vpsllvq ymm10,ymm1,ymm2
  2d:	c4 62 f5 47 da       	vpsllvq ymm11,ymm1,ymm2
  32:	c4 62 f5 47 e2       	vpsllvq ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 5.51
- Reference cycles: 3.27
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 5.5
- UOPS_PORT_1: 5.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 f5 47 c2       	vpsllvq ymm0,ymm1,ymm2
   5:	c4 e2 f5 47 da       	vpsllvq ymm3,ymm1,ymm2
   a:	c4 e2 f5 47 e2       	vpsllvq ymm4,ymm1,ymm2
   f:	c4 e2 f5 47 ea       	vpsllvq ymm5,ymm1,ymm2
  14:	c4 e2 f5 47 f2       	vpsllvq ymm6,ymm1,ymm2
  19:	c4 e2 f5 47 fa       	vpsllvq ymm7,ymm1,ymm2
  1e:	c4 62 f5 47 c2       	vpsllvq ymm8,ymm1,ymm2
  23:	c4 62 f5 47 ca       	vpsllvq ymm9,ymm1,ymm2
  28:	c4 62 f5 47 d2       	vpsllvq ymm10,ymm1,ymm2
  2d:	c4 62 f5 47 da       	vpsllvq ymm11,ymm1,ymm2
  32:	c4 62 f5 47 e2       	vpsllvq ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 5.51
- Reference cycles: 3.29
- UOPS_EXECUTED.THREAD: 11.1
- RETIRE_SLOTS: 11.1
- UOPS_MITE: 0.11
- UOPS_MS: 0.02
- UOPS_PORT_0: 5.5
- UOPS_PORT_1: 5.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.58
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.6
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.6
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.28
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.19
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 1.2
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.01
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7
  28:	c4 42 bd 47 c0       	vpsllvq ymm8,ymm8,ymm8
  2d:	c4 42 b5 47 c9       	vpsllvq ymm9,ymm9,ymm9
  32:	c4 42 ad 47 d2       	vpsllvq ymm10,ymm10,ymm10
  37:	c4 42 a5 47 db       	vpsllvq ymm11,ymm11,ymm11
  3c:	c4 42 9d 47 e4       	vpsllvq ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.5
- Reference cycles: 4.02
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7
  28:	c4 42 bd 47 c0       	vpsllvq ymm8,ymm8,ymm8
  2d:	c4 42 b5 47 c9       	vpsllvq ymm9,ymm9,ymm9
  32:	c4 42 ad 47 d2       	vpsllvq ymm10,ymm10,ymm10
  37:	c4 42 a5 47 db       	vpsllvq ymm11,ymm11,ymm11
  3c:	c4 42 9d 47 e4       	vpsllvq ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 6.51
- Reference cycles: 3.88
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 fd 47 c0       	vpsllvq ymm0,ymm0,ymm0
   5:	c4 e2 f5 47 c9       	vpsllvq ymm1,ymm1,ymm1
   a:	c4 e2 ed 47 d2       	vpsllvq ymm2,ymm2,ymm2
   f:	c4 e2 e5 47 db       	vpsllvq ymm3,ymm3,ymm3
  14:	c4 e2 dd 47 e4       	vpsllvq ymm4,ymm4,ymm4
  19:	c4 e2 d5 47 ed       	vpsllvq ymm5,ymm5,ymm5
  1e:	c4 e2 cd 47 f6       	vpsllvq ymm6,ymm6,ymm6
  23:	c4 e2 c5 47 ff       	vpsllvq ymm7,ymm7,ymm7
  28:	c4 42 bd 47 c0       	vpsllvq ymm8,ymm8,ymm8
  2d:	c4 42 b5 47 c9       	vpsllvq ymm9,ymm9,ymm9
  32:	c4 42 ad 47 d2       	vpsllvq ymm10,ymm10,ymm10
  37:	c4 42 a5 47 db       	vpsllvq ymm11,ymm11,ymm11
  3c:	c4 42 9d 47 e4       	vpsllvq ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.51
- Reference cycles: 3.88
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

VPSLLVQ (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10