VPOR (XMM, XMM, XMM)

With unroll_count=500 and no inner loop

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.35
- Reference cycles: 0.24
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.33
- Reference cycles: 0.2
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.33
- Reference cycles: 0.2
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.33
- Reference cycles: 0.55
- UOPS_EXECUTED.THREAD: 4.02
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.34
- UOPS_PORT_1: 1.32
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With loop_count=1000 and unroll_count=2

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.34
- Reference cycles: 0.79
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.33
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.34
- Reference cycles: 0.82
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.33
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.65
- Reference cycles: 1.7
- UOPS_EXECUTED.THREAD: 8.03
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.64
- UOPS_PORT_5: 2.68
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.98

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.68
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 1.61
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2
  20:	c5 71 eb d2          	vpor   xmm10,xmm1,xmm2
  24:	c5 71 eb da          	vpor   xmm11,xmm1,xmm2
  28:	c5 71 eb e2          	vpor   xmm12,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 3.66
- Reference cycles: 2.19
- UOPS_EXECUTED.THREAD: 11.03
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 11.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.67
- UOPS_PORT_1: 3.64
- UOPS_PORT_5: 3.68
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.73

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2
  20:	c5 71 eb d2          	vpor   xmm10,xmm1,xmm2
  24:	c5 71 eb da          	vpor   xmm11,xmm1,xmm2
  28:	c5 71 eb e2          	vpor   xmm12,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 3.68
- Reference cycles: 2.19
- UOPS_EXECUTED.THREAD: 12.01
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 3.67
- UOPS_PORT_1: 3.67
- UOPS_PORT_5: 3.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f1 eb c2          	vpor   xmm0,xmm1,xmm2
   4:	c5 f1 eb da          	vpor   xmm3,xmm1,xmm2
   8:	c5 f1 eb e2          	vpor   xmm4,xmm1,xmm2
   c:	c5 f1 eb ea          	vpor   xmm5,xmm1,xmm2
  10:	c5 f1 eb f2          	vpor   xmm6,xmm1,xmm2
  14:	c5 f1 eb fa          	vpor   xmm7,xmm1,xmm2
  18:	c5 71 eb c2          	vpor   xmm8,xmm1,xmm2
  1c:	c5 71 eb ca          	vpor   xmm9,xmm1,xmm2
  20:	c5 71 eb d2          	vpor   xmm10,xmm1,xmm2
  24:	c5 71 eb da          	vpor   xmm11,xmm1,xmm2
  28:	c5 71 eb e2          	vpor   xmm12,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 3.68
- Reference cycles: 2.19
- UOPS_EXECUTED.THREAD: 11.1
- RETIRE_SLOTS: 11.1
- UOPS_MITE: 0.11
- UOPS_MS: 0.02
- UOPS_PORT_0: 3.67
- UOPS_PORT_1: 3.67
- UOPS_PORT_5: 3.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.58
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.34
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.6
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.6
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.5
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 3.99
- RETIRE_SLOTS: 4.02
- UOPS_MITE: 3.97
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.34
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.49
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.5
- Reference cycles: 0.89
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.67
- Reference cycles: 1.58
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.66
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.68
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.03
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 1.61
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7
  20:	c4 41 39 eb c0       	vpor   xmm8,xmm8,xmm8
  25:	c4 41 31 eb c9       	vpor   xmm9,xmm9,xmm9
  2a:	c4 41 29 eb d2       	vpor   xmm10,xmm10,xmm10
  2f:	c4 41 21 eb db       	vpor   xmm11,xmm11,xmm11
  34:	c4 41 19 eb e4       	vpor   xmm12,xmm12,xmm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.32
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.33
- UOPS_PORT_1: 4.34
- UOPS_PORT_5: 4.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7
  20:	c4 41 39 eb c0       	vpor   xmm8,xmm8,xmm8
  25:	c4 41 31 eb c9       	vpor   xmm9,xmm9,xmm9
  2a:	c4 41 29 eb d2       	vpor   xmm10,xmm10,xmm10
  2f:	c4 41 21 eb db       	vpor   xmm11,xmm11,xmm11
  34:	c4 41 19 eb e4       	vpor   xmm12,xmm12,xmm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 4.34
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.33
- UOPS_PORT_1: 4.33
- UOPS_PORT_5: 4.33
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f9 eb c0          	vpor   xmm0,xmm0,xmm0
   4:	c5 f1 eb c9          	vpor   xmm1,xmm1,xmm1
   8:	c5 e9 eb d2          	vpor   xmm2,xmm2,xmm2
   c:	c5 e1 eb db          	vpor   xmm3,xmm3,xmm3
  10:	c5 d9 eb e4          	vpor   xmm4,xmm4,xmm4
  14:	c5 d1 eb ed          	vpor   xmm5,xmm5,xmm5
  18:	c5 c9 eb f6          	vpor   xmm6,xmm6,xmm6
  1c:	c5 c1 eb ff          	vpor   xmm7,xmm7,xmm7
  20:	c4 41 39 eb c0       	vpor   xmm8,xmm8,xmm8
  25:	c4 41 31 eb c9       	vpor   xmm9,xmm9,xmm9
  2a:	c4 41 29 eb d2       	vpor   xmm10,xmm10,xmm10
  2f:	c4 41 21 eb db       	vpor   xmm11,xmm11,xmm11
  34:	c4 41 19 eb e4       	vpor   xmm12,xmm12,xmm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 4.34
- Reference cycles: 2.58
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.33
- UOPS_PORT_1: 4.33
- UOPS_PORT_5: 4.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

VPOR (XMM, XMM, XMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10