VADDPD (ZMM, K, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.44
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.44
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.45
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.45
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 4.62
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 4.89
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 4.89
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 10.1
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 9.78
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 9.78
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.44
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.44
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VADDPD (ZMM, K, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100