RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 44.0
- Reference cycles: 26.28
- UOPS_EXECUTED.THREAD: 46.0
- RETIRE_SLOTS: 53.0
- UOPS_MITE: 0.0
- UOPS_MS: 53.0
- UOPS_PORT_0: 11.0
- UOPS_PORT_1: 10.0
- UOPS_PORT_5: 10.0
- UOPS_PORT_6: 15.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 44.0
- Reference cycles: 26.3
- UOPS_EXECUTED.THREAD: 46.0
- RETIRE_SLOTS: 54.0
- UOPS_MITE: 1.0
- UOPS_MS: 53.0
- UOPS_PORT_0: 11.0
- UOPS_PORT_1: 10.0
- UOPS_PORT_5: 10.0
- UOPS_PORT_6: 15.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=1000 and unroll_count=10
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.2
- Core cycles: 44.1
- Reference cycles: 26.36
- UOPS_EXECUTED.THREAD: 46.1
- RETIRE_SLOTS: 53.1
- UOPS_MITE: 0.1
- UOPS_MS: 53.0
- UOPS_PORT_0: 11.1
- UOPS_PORT_1: 9.9
- UOPS_PORT_5: 10.1
- UOPS_PORT_6: 15.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1
With loop_count=100 and unroll_count=100
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.02
- Core cycles: 44.01
- Reference cycles: 26.31
- UOPS_EXECUTED.THREAD: 46.01
- RETIRE_SLOTS: 53.01
- UOPS_MITE: 0.01
- UOPS_MS: 53.0
- UOPS_PORT_0: 11.01
- UOPS_PORT_1: 9.99
- UOPS_PORT_5: 10.01
- UOPS_PORT_6: 15.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01