ADDSD (XMM, M64)

With unroll_count=500 and no inner loop

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.19
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.42
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.05
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.13
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.84
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 8.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.98

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.42
- Reference cycles: 2.65
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 8.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.23
- Reference cycles: 2.48
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.1
- UOPS_MS: 0.02
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.02
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 8.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]
  2f:	f2 45 0f 58 46 40    	addsd  xmm8,QWORD PTR [r14+0x40]
  35:	f2 45 0f 58 4e 48    	addsd  xmm9,QWORD PTR [r14+0x48]
  3b:	f2 45 0f 58 56 50    	addsd  xmm10,QWORD PTR [r14+0x50]
  41:	f2 45 0f 58 5e 58    	addsd  xmm11,QWORD PTR [r14+0x58]
  47:	f2 45 0f 58 66 60    	addsd  xmm12,QWORD PTR [r14+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.5
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 26.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]
  2f:	f2 45 0f 58 46 40    	addsd  xmm8,QWORD PTR [r14+0x40]
  35:	f2 45 0f 58 4e 48    	addsd  xmm9,QWORD PTR [r14+0x48]
  3b:	f2 45 0f 58 56 50    	addsd  xmm10,QWORD PTR [r14+0x50]
  41:	f2 45 0f 58 5e 58    	addsd  xmm11,QWORD PTR [r14+0x58]
  47:	f2 45 0f 58 66 60    	addsd  xmm12,QWORD PTR [r14+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 6.52
- Reference cycles: 3.87
- UOPS_EXECUTED.THREAD: 27.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	f2 41 0f 58 4e 08    	addsd  xmm1,QWORD PTR [r14+0x8]
   b:	f2 41 0f 58 56 10    	addsd  xmm2,QWORD PTR [r14+0x10]
  11:	f2 41 0f 58 5e 18    	addsd  xmm3,QWORD PTR [r14+0x18]
  17:	f2 41 0f 58 66 20    	addsd  xmm4,QWORD PTR [r14+0x20]
  1d:	f2 41 0f 58 6e 28    	addsd  xmm5,QWORD PTR [r14+0x28]
  23:	f2 41 0f 58 76 30    	addsd  xmm6,QWORD PTR [r14+0x30]
  29:	f2 41 0f 58 7e 38    	addsd  xmm7,QWORD PTR [r14+0x38]
  2f:	f2 45 0f 58 46 40    	addsd  xmm8,QWORD PTR [r14+0x40]
  35:	f2 45 0f 58 4e 48    	addsd  xmm9,QWORD PTR [r14+0x48]
  3b:	f2 45 0f 58 56 50    	addsd  xmm10,QWORD PTR [r14+0x50]
  41:	f2 45 0f 58 5e 58    	addsd  xmm11,QWORD PTR [r14+0x58]
  47:	f2 45 0f 58 66 60    	addsd  xmm12,QWORD PTR [r14+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.52
- Reference cycles: 3.88
- UOPS_EXECUTED.THREAD: 26.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.95
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.49
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.92
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.37
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.4
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.06
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.13
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 8.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.42
- Reference cycles: 2.64
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 8.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.25
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.02
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 8.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	f2 47 0f 58 44 2e 40 	addsd  xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	f2 47 0f 58 4c 2e 48 	addsd  xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	f2 47 0f 58 54 2e 50 	addsd  xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	f2 47 0f 58 5c 2e 58 	addsd  xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	f2 47 0f 58 64 2e 60 	addsd  xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.5
- Reference cycles: 4.02
- UOPS_EXECUTED.THREAD: 26.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.27

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	f2 47 0f 58 44 2e 40 	addsd  xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	f2 47 0f 58 4c 2e 48 	addsd  xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	f2 47 0f 58 54 2e 50 	addsd  xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	f2 47 0f 58 5c 2e 58 	addsd  xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	f2 47 0f 58 64 2e 60 	addsd  xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 6.52
- Reference cycles: 3.87
- UOPS_EXECUTED.THREAD: 27.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	f2 43 0f 58 4c 2e 08 	addsd  xmm1,QWORD PTR [r14+r13*1+0x8]
   d:	f2 43 0f 58 54 2e 10 	addsd  xmm2,QWORD PTR [r14+r13*1+0x10]
  14:	f2 43 0f 58 5c 2e 18 	addsd  xmm3,QWORD PTR [r14+r13*1+0x18]
  1b:	f2 43 0f 58 64 2e 20 	addsd  xmm4,QWORD PTR [r14+r13*1+0x20]
  22:	f2 43 0f 58 6c 2e 28 	addsd  xmm5,QWORD PTR [r14+r13*1+0x28]
  29:	f2 43 0f 58 74 2e 30 	addsd  xmm6,QWORD PTR [r14+r13*1+0x30]
  30:	f2 43 0f 58 7c 2e 38 	addsd  xmm7,QWORD PTR [r14+r13*1+0x38]
  37:	f2 47 0f 58 44 2e 40 	addsd  xmm8,QWORD PTR [r14+r13*1+0x40]
  3e:	f2 47 0f 58 4c 2e 48 	addsd  xmm9,QWORD PTR [r14+r13*1+0x48]
  45:	f2 47 0f 58 54 2e 50 	addsd  xmm10,QWORD PTR [r14+r13*1+0x50]
  4c:	f2 47 0f 58 5c 2e 58 	addsd  xmm11,QWORD PTR [r14+r13*1+0x58]
  53:	f2 47 0f 58 64 2e 60 	addsd  xmm12,QWORD PTR [r14+r13*1+0x60]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOV [R14+16], RAX;
MOVUPD XMM3, [R14];
MOV [R14+24], RAX;
MOVUPD XMM4, [R14];
MOV [R14+32], RAX;
MOVUPD XMM5, [R14];
MOV [R14+40], RAX;
MOVUPD XMM6, [R14];
MOV [R14+48], RAX;
MOVUPD XMM7, [R14];
MOV [R14+56], RAX;
MOVUPD XMM8, [R14];
MOV [R14+64], RAX;
MOVUPD XMM9, [R14];
MOV [R14+72], RAX;
MOVUPD XMM10, [R14];
MOV [R14+80], RAX;
MOVUPD XMM11, [R14];
MOV [R14+88], RAX;
MOVUPD XMM12, [R14];
MOV [R14+96], RAX

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.52
- Reference cycles: 3.89
- UOPS_EXECUTED.THREAD: 26.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 13.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

ADDSD (XMM, M64) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10