VSQRTPS (XMM, XMM) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 10.0
  • Reference cycles: 10.01
  • UOPS_RETIRED.ALL: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 3.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.25
  • Reference cycles: 18.24
  • UOPS_RETIRED.ALL: 3.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 3.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 10.05
  • Reference cycles: 10.05
  • UOPS_RETIRED.ALL: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.1
  • DIV_CYCLES: 3.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 10.01
  • Reference cycles: 10.01
  • UOPS_RETIRED.ALL: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • DIV_CYCLES: 3.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 40.0
  • Reference cycles: 39.95
  • UOPS_RETIRED.ALL: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 12.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 40.21
  • Reference cycles: 40.21
  • UOPS_RETIRED.ALL: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.5
  • DIV_CYCLES: 12.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 40.03
  • Reference cycles: 40.03
  • UOPS_RETIRED.ALL: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.05
  • DIV_CYCLES: 12.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 80.0
  • Reference cycles: 79.9
  • UOPS_RETIRED.ALL: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 24.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 80.43
  • Reference cycles: 80.43
  • UOPS_RETIRED.ALL: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 24.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 80.05
  • Reference cycles: 80.07
  • UOPS_RETIRED.ALL: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.1
  • DIV_CYCLES: 24.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 14.0
  • Reference cycles: 14.01
  • UOPS_RETIRED.ALL: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 7.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 22.25
  • Reference cycles: 22.25
  • UOPS_RETIRED.ALL: 3.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 7.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 14.05
  • Reference cycles: 14.05
  • UOPS_RETIRED.ALL: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.1
  • DIV_CYCLES: 7.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 14.0
  • Reference cycles: 14.0
  • UOPS_RETIRED.ALL: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • DIV_CYCLES: 7.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 56.01
  • Reference cycles: 55.93
  • UOPS_RETIRED.ALL: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 28.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 56.22
  • Reference cycles: 56.21
  • UOPS_RETIRED.ALL: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.5
  • DIV_CYCLES: 28.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 56.03
  • Reference cycles: 56.03
  • UOPS_RETIRED.ALL: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.05
  • DIV_CYCLES: 28.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 112.01
  • Reference cycles: 111.92
  • UOPS_RETIRED.ALL: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 56.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 112.43
  • Reference cycles: 112.43
  • UOPS_RETIRED.ALL: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 56.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c5 f8 51 d0          	vsqrtps xmm2,xmm0
     4:	c5 f8 51 d8          	vsqrtps xmm3,xmm0
     8:	c5 f8 51 e0          	vsqrtps xmm4,xmm0
     c:	c5 f8 51 e8          	vsqrtps xmm5,xmm0
    10:	c5 f8 51 f0          	vsqrtps xmm6,xmm0
    14:	c5 f8 51 f8          	vsqrtps xmm7,xmm0
    18:	c5 78 51 c0          	vsqrtps xmm8,xmm0
    1c:	c5 78 51 c8          	vsqrtps xmm9,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 112.05
  • Reference cycles: 112.06
  • UOPS_RETIRED.ALL: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.1
  • DIV_CYCLES: 56.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02