VCVTDQ2PS (YMM, YMM) - Throughput and Uops (IACA 2.3)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 1.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm0, ymm1
Total Num Of Uops: 1

With 12 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 12.00 Cycles       Throughput Bottleneck: Backend. Port1

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 12.0 | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm0, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm2, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm3, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm4, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm5, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm6, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm7, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm8, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm9, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm10, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm11, ymm1
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm12, ymm1
Total Num Of Uops: 12

With the same register for for different operands

Throughput Analysis Report
--------------------------
Block Throughput: 2.86 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 1.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   1    |           | 1.0 |           |           |     |     | CP | vcvtdq2ps ymm0, ymm0
Total Num Of Uops: 1