ROL (R32, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 1.02
  • UOPS_RETIRED.ALL: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.55
  • Reference cycles: 1.56
  • UOPS_RETIRED.ALL: 3.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	90                   	nop
     5:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 1.01
  • UOPS_RETIRED.ALL: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	90                   	nop
     5:	90                   	nop
     6:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 2.0
  • Reference cycles: 1.98
  • UOPS_RETIRED.ALL: 5.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.06
  • Reference cycles: 1.06
  • UOPS_RETIRED.ALL: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.04
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.06
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.01
  • Reference cycles: 1.02
  • UOPS_RETIRED.ALL: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.94
  • UOPS_RETIRED.ALL: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.32
  • Reference cycles: 4.32
  • UOPS_RETIRED.ALL: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.21
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.29
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.23
  • Reference cycles: 4.23
  • UOPS_RETIRED.ALL: 8.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.02
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.03
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 8.16
  • UOPS_RETIRED.ALL: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.53
  • Reference cycles: 8.52
  • UOPS_RETIRED.ALL: 17.0
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.51
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.51
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.37
  • Reference cycles: 8.37
  • UOPS_RETIRED.ALL: 16.1
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.03
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.08
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
    1f:	c1 c1 02             	rol    ecx,0x2
    22:	c1 c2 02             	rol    edx,0x2
    25:	c1 c7 02             	rol    edi,0x2
    28:	c1 c6 02             	rol    esi,0x2
    2b:	c1 c5 02             	rol    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 13.0
  • Reference cycles: 12.92
  • UOPS_RETIRED.ALL: 26.0
  • RETIRE_SLOTS: 26.0
  • UOPS_MITE: 26.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 13.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
    1f:	c1 c1 02             	rol    ecx,0x2
    22:	c1 c2 02             	rol    edx,0x2
    25:	c1 c7 02             	rol    edi,0x2
    28:	c1 c6 02             	rol    esi,0x2
    2b:	c1 c5 02             	rol    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 13.55
  • Reference cycles: 13.56
  • UOPS_RETIRED.ALL: 27.0
  • RETIRE_SLOTS: 27.0
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 13.54
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.46
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 c0 02          	rol    r8d,0x2
     4:	41 c1 c1 02          	rol    r9d,0x2
     8:	41 c1 c2 02          	rol    r10d,0x2
     c:	41 c1 c3 02          	rol    r11d,0x2
    10:	41 c1 c4 02          	rol    r12d,0x2
    14:	41 c1 c5 02          	rol    r13d,0x2
    18:	41 c1 c6 02          	rol    r14d,0x2
    1c:	c1 c3 02             	rol    ebx,0x2
    1f:	c1 c1 02             	rol    ecx,0x2
    22:	c1 c2 02             	rol    edx,0x2
    25:	c1 c7 02             	rol    edi,0x2
    28:	c1 c6 02             	rol    esi,0x2
    2b:	c1 c5 02             	rol    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 13.31
  • Reference cycles: 13.32
  • UOPS_RETIRED.ALL: 26.1
  • RETIRE_SLOTS: 26.1
  • UOPS_MITE: 10.06
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 12.99
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.11
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.98