RDTSC - Throughput and Uops

With unroll_count=500 and no inner loop

Code:
```
   0:	0f 31                	rdtsc  
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 28.0
- Reference cycles: 28.02
- UOPS_RETIRED.ALL: 21.0
- RETIRE_SLOTS: 21.0
- UOPS_MITE: 0.0
- UOPS_MS: 21.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 5.75
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.75
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	0f 31                	rdtsc  
   2:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 28.0
- Reference cycles: 27.98
- UOPS_RETIRED.ALL: 22.0
- RETIRE_SLOTS: 22.0
- UOPS_MITE: 1.0
- UOPS_MS: 21.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:
```
   0:	0f 31                	rdtsc  
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 28.0
- Reference cycles: 28.0
- UOPS_RETIRED.ALL: 21.1
- RETIRE_SLOTS: 21.1
- UOPS_MITE: 0.1
- UOPS_MS: 21.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 5.73
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.87
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

Code:
```
   0:	0f 31                	rdtsc  
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 28.0
- Reference cycles: 28.0
- UOPS_RETIRED.ALL: 21.01
- RETIRE_SLOTS: 21.01
- UOPS_MITE: 0.01
- UOPS_MS: 21.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 5.75
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.76
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01