RDMSR - Throughput and Uops

With unroll_count=500 and no inner loop

Code:
```
   0:	0f 32                	rdmsr  
```
Init:
```
MOV RCX, 0xE7
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 104.5
- Reference cycles: 104.5
- UOPS_RETIRED.ALL: 77.0
- RETIRE_SLOTS: 77.0
- UOPS_MITE: 0.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 22.0
- UOPS_PORT_1: 17.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 43.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	0f 32                	rdmsr  
   2:	90                   	nop

Init:
```
MOV RCX, 0xE7
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 105.67
- Reference cycles: 105.67
- UOPS_RETIRED.ALL: 78.0
- RETIRE_SLOTS: 78.0
- UOPS_MITE: 1.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 22.0
- UOPS_PORT_1: 17.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 43.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=10 and unroll_count=1

Code:
```
   0:	0f 32                	rdmsr  
```
Init:
```
MOV RCX, 0xE7
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 105.43
- Reference cycles: 104.83
- UOPS_RETIRED.ALL: 78.0
- RETIRE_SLOTS: 78.0
- UOPS_MITE: 1.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 22.0
- UOPS_PORT_1: 17.1
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 43.8
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.2

With loop_count=10 and unroll_count=1

Code:
```
   0:	0f 32                	rdmsr  
```
Init:
```
MOV RCX, 0xE7
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 105.33
- Reference cycles: 105.97
- UOPS_RETIRED.ALL: 78.0
- RETIRE_SLOTS: 78.0
- UOPS_MITE: 1.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 22.0
- UOPS_PORT_1: 17.1
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 43.8
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.2