RCL (R32, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 6.0
  • Reference cycles: 6.05
  • UOPS_RETIRED.ALL: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 2.5
  • UOPS_PORT_1: 2.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.25
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.0
  • UOPS_RETIRED.ALL: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 3.0
  • UOPS_PORT_1: 2.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 6.1
  • Reference cycles: 6.1
  • UOPS_RETIRED.ALL: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 2.1
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 2.9
  • UOPS_PORT_1: 1.75
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.45
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.1

With loop_count=100 and unroll_count=100

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 6.01
  • Reference cycles: 6.01
  • UOPS_RETIRED.ALL: 8.01
  • RETIRE_SLOTS: 8.01
  • UOPS_MITE: 2.01
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 2.99
  • UOPS_PORT_1: 1.68
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.35
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.0
  • UOPS_RETIRED.ALL: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 3.0
  • UOPS_PORT_1: 3.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 7.1
  • Reference cycles: 7.1
  • UOPS_RETIRED.ALL: 9.1
  • RETIRE_SLOTS: 9.1
  • UOPS_MITE: 3.1
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 3.0
  • UOPS_PORT_1: 2.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.1
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.1

With loop_count=100 and unroll_count=100

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 7.01
  • Reference cycles: 7.01
  • UOPS_RETIRED.ALL: 9.01
  • RETIRE_SLOTS: 9.01
  • UOPS_MITE: 3.01
  • UOPS_MS: 6.0
  • UOPS_PORT_0: 3.0
  • UOPS_PORT_1: 2.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.01

With unroll_count=200 and no inner loop

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 24.0
  • Reference cycles: 24.08
  • UOPS_RETIRED.ALL: 32.0
  • RETIRE_SLOTS: 32.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 24.0
  • UOPS_PORT_0: 10.0
  • UOPS_PORT_1: 9.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 24.51
  • Reference cycles: 24.51
  • UOPS_RETIRED.ALL: 32.5
  • RETIRE_SLOTS: 32.5
  • UOPS_MITE: 8.5
  • UOPS_MS: 24.01
  • UOPS_PORT_0: 11.0
  • UOPS_PORT_1: 7.5
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 14.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.5

With loop_count=100 and unroll_count=20

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 24.06
  • Reference cycles: 24.05
  • UOPS_RETIRED.ALL: 32.05
  • RETIRE_SLOTS: 32.05
  • UOPS_MITE: 8.05
  • UOPS_MS: 24.01
  • UOPS_PORT_0: 11.88
  • UOPS_PORT_1: 6.77
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.4
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.05

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 28.0
  • Reference cycles: 28.02
  • UOPS_RETIRED.ALL: 36.0
  • RETIRE_SLOTS: 36.0
  • UOPS_MITE: 12.0
  • UOPS_MS: 24.0
  • UOPS_PORT_0: 12.0
  • UOPS_PORT_1: 12.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 12.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 28.51
  • Reference cycles: 28.51
  • UOPS_RETIRED.ALL: 36.5
  • RETIRE_SLOTS: 36.5
  • UOPS_MITE: 12.5
  • UOPS_MS: 24.0
  • UOPS_PORT_0: 12.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 16.5
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.5

With loop_count=100 and unroll_count=20

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.1
  • Core cycles: 28.05
  • Reference cycles: 28.05
  • UOPS_RETIRED.ALL: 36.05
  • RETIRE_SLOTS: 36.05
  • UOPS_MITE: 12.05
  • UOPS_MS: 24.0
  • UOPS_PORT_0: 12.0
  • UOPS_PORT_1: 8.04
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 16.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.05

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 48.0
  • Reference cycles: 48.17
  • UOPS_RETIRED.ALL: 64.0
  • RETIRE_SLOTS: 64.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 48.0
  • UOPS_PORT_0: 20.0
  • UOPS_PORT_1: 18.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 26.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 49.01
  • Reference cycles: 49.02
  • UOPS_RETIRED.ALL: 65.0
  • RETIRE_SLOTS: 65.0
  • UOPS_MITE: 17.0
  • UOPS_MS: 48.01
  • UOPS_PORT_0: 22.01
  • UOPS_PORT_1: 15.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 28.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 9.0

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 48.11
  • Reference cycles: 48.1
  • UOPS_RETIRED.ALL: 64.1
  • RETIRE_SLOTS: 64.1
  • UOPS_MITE: 16.1
  • UOPS_MS: 48.01
  • UOPS_PORT_0: 23.76
  • UOPS_PORT_1: 13.54
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 26.81
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.11

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 56.0
  • Reference cycles: 55.87
  • UOPS_RETIRED.ALL: 72.0
  • RETIRE_SLOTS: 72.0
  • UOPS_MITE: 24.0
  • UOPS_MS: 48.0
  • UOPS_PORT_0: 24.0
  • UOPS_PORT_1: 24.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 24.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 57.01
  • Reference cycles: 57.01
  • UOPS_RETIRED.ALL: 73.0
  • RETIRE_SLOTS: 73.0
  • UOPS_MITE: 25.01
  • UOPS_MS: 48.01
  • UOPS_PORT_0: 24.0
  • UOPS_PORT_1: 16.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 33.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 17.01

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 56.11
  • Reference cycles: 56.09
  • UOPS_RETIRED.ALL: 72.1
  • RETIRE_SLOTS: 72.1
  • UOPS_MITE: 24.1
  • UOPS_MS: 48.01
  • UOPS_PORT_0: 24.0
  • UOPS_PORT_1: 16.08
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 32.02
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.11

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
    1f:	c1 d1 02             	rcl    ecx,0x2
    22:	c1 d2 02             	rcl    edx,0x2
    25:	c1 d7 02             	rcl    edi,0x2
    28:	c1 d6 02             	rcl    esi,0x2
    2b:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 78.0
  • Reference cycles: 77.86
  • UOPS_RETIRED.ALL: 104.0
  • RETIRE_SLOTS: 104.0
  • UOPS_MITE: 26.0
  • UOPS_MS: 78.0
  • UOPS_PORT_0: 32.5
  • UOPS_PORT_1: 29.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 42.25
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
    1f:	c1 d1 02             	rcl    ecx,0x2
    22:	c1 d2 02             	rcl    edx,0x2
    25:	c1 d7 02             	rcl    edi,0x2
    28:	c1 d6 02             	rcl    esi,0x2
    2b:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 79.01
  • Reference cycles: 79.02
  • UOPS_RETIRED.ALL: 105.0
  • RETIRE_SLOTS: 105.0
  • UOPS_MITE: 27.0
  • UOPS_MS: 78.01
  • UOPS_PORT_0: 37.99
  • UOPS_PORT_1: 22.51
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 44.5
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 14.0

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 d0 02          	rcl    r8d,0x2
     4:	41 c1 d1 02          	rcl    r9d,0x2
     8:	41 c1 d2 02          	rcl    r10d,0x2
     c:	41 c1 d3 02          	rcl    r11d,0x2
    10:	41 c1 d4 02          	rcl    r12d,0x2
    14:	41 c1 d5 02          	rcl    r13d,0x2
    18:	41 c1 d6 02          	rcl    r14d,0x2
    1c:	c1 d3 02             	rcl    ebx,0x2
    1f:	c1 d1 02             	rcl    ecx,0x2
    22:	c1 d2 02             	rcl    edx,0x2
    25:	c1 d7 02             	rcl    edi,0x2
    28:	c1 d6 02             	rcl    esi,0x2
    2b:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 78.11
  • Reference cycles: 78.13
  • UOPS_RETIRED.ALL: 104.1
  • RETIRE_SLOTS: 104.1
  • UOPS_MITE: 26.1
  • UOPS_MS: 78.01
  • UOPS_PORT_0: 38.77
  • UOPS_PORT_1: 21.91
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 43.42
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
    37:	4d 85 ff             	test   r15,r15
    3a:	c1 d1 02             	rcl    ecx,0x2
    3d:	4d 85 ff             	test   r15,r15
    40:	c1 d2 02             	rcl    edx,0x2
    43:	4d 85 ff             	test   r15,r15
    46:	c1 d7 02             	rcl    edi,0x2
    49:	4d 85 ff             	test   r15,r15
    4c:	c1 d6 02             	rcl    esi,0x2
    4f:	4d 85 ff             	test   r15,r15
    52:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 26.0
  • Core cycles: 91.12
  • Reference cycles: 91.01
  • UOPS_RETIRED.ALL: 117.0
  • RETIRE_SLOTS: 117.0
  • UOPS_MITE: 39.03
  • UOPS_MS: 78.0
  • UOPS_PORT_0: 39.01
  • UOPS_PORT_1: 31.2
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 46.79
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 26.01

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
    37:	4d 85 ff             	test   r15,r15
    3a:	c1 d1 02             	rcl    ecx,0x2
    3d:	4d 85 ff             	test   r15,r15
    40:	c1 d2 02             	rcl    edx,0x2
    43:	4d 85 ff             	test   r15,r15
    46:	c1 d7 02             	rcl    edi,0x2
    49:	4d 85 ff             	test   r15,r15
    4c:	c1 d6 02             	rcl    esi,0x2
    4f:	4d 85 ff             	test   r15,r15
    52:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 28.0
  • Core cycles: 92.01
  • Reference cycles: 92.02
  • UOPS_RETIRED.ALL: 118.0
  • RETIRE_SLOTS: 118.0
  • UOPS_MITE: 40.01
  • UOPS_MS: 78.01
  • UOPS_PORT_0: 39.0
  • UOPS_PORT_1: 26.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 52.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 27.01

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 85 ff             	test   r15,r15
     3:	41 c1 d0 02          	rcl    r8d,0x2
     7:	4d 85 ff             	test   r15,r15
     a:	41 c1 d1 02          	rcl    r9d,0x2
     e:	4d 85 ff             	test   r15,r15
    11:	41 c1 d2 02          	rcl    r10d,0x2
    15:	4d 85 ff             	test   r15,r15
    18:	41 c1 d3 02          	rcl    r11d,0x2
    1c:	4d 85 ff             	test   r15,r15
    1f:	41 c1 d4 02          	rcl    r12d,0x2
    23:	4d 85 ff             	test   r15,r15
    26:	41 c1 d5 02          	rcl    r13d,0x2
    2a:	4d 85 ff             	test   r15,r15
    2d:	41 c1 d6 02          	rcl    r14d,0x2
    31:	4d 85 ff             	test   r15,r15
    34:	c1 d3 02             	rcl    ebx,0x2
    37:	4d 85 ff             	test   r15,r15
    3a:	c1 d1 02             	rcl    ecx,0x2
    3d:	4d 85 ff             	test   r15,r15
    40:	c1 d2 02             	rcl    edx,0x2
    43:	4d 85 ff             	test   r15,r15
    46:	c1 d7 02             	rcl    edi,0x2
    49:	4d 85 ff             	test   r15,r15
    4c:	c1 d6 02             	rcl    esi,0x2
    4f:	4d 85 ff             	test   r15,r15
    52:	c1 d5 02             	rcl    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 26.2
  • Core cycles: 91.11
  • Reference cycles: 91.11
  • UOPS_RETIRED.ALL: 117.1
  • RETIRE_SLOTS: 117.1
  • UOPS_MITE: 39.11
  • UOPS_MS: 78.01
  • UOPS_PORT_0: 39.0
  • UOPS_PORT_1: 26.13
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 51.97
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 26.11