CMOVBE (R32, R32)

With unroll_count=500 and no inner loop

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.03
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.97
- UOPS_RETIRED.ALL: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.2
- UOPS_PORT_1: 0.6
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.2
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 1.1
- UOPS_RETIRED.ALL: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.08
- UOPS_PORT_1: 0.92
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.1

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 1.1
- UOPS_RETIRED.ALL: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.05
- UOPS_PORT_1: 0.95
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.04
- Reference cycles: 1.04
- UOPS_RETIRED.ALL: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.03
- UOPS_PORT_1: 0.95
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.05
- Reference cycles: 1.05
- UOPS_RETIRED.ALL: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.04
- UOPS_PORT_1: 0.92
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.05
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.18
- Reference cycles: 4.22
- UOPS_RETIRED.ALL: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.18
- UOPS_PORT_1: 3.65
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.17
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.51
- Reference cycles: 4.51
- UOPS_RETIRED.ALL: 12.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 12.52
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.34
- UOPS_PORT_1: 3.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.51

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.61
- Reference cycles: 4.61
- UOPS_RETIRED.ALL: 12.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.25
- UOPS_PORT_1: 3.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.59
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.22
- Reference cycles: 4.22
- UOPS_RETIRED.ALL: 12.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 12.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.18
- UOPS_PORT_1: 3.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.2
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.06

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.25
- Reference cycles: 4.25
- UOPS_RETIRED.ALL: 12.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.2
- UOPS_PORT_1: 3.62
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.24
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.35
- Reference cycles: 8.44
- UOPS_RETIRED.ALL: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.35
- UOPS_PORT_1: 7.3
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.03
- Reference cycles: 9.03
- UOPS_RETIRED.ALL: 25.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 25.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.67
- UOPS_PORT_1: 7.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 9.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 9.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d
  20:	40                   	rex
  21:	40                   	rex
  22:	40                   	rex
  23:	40                   	rex
  24:	45 0f 46 e9          	cmovbe r13d,r9d
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	45 0f 46 f1          	cmovbe r14d,r9d
  30:	40                   	rex
  31:	40                   	rex
  32:	40                   	rex
  33:	40                   	rex
  34:	41 0f 46 d9          	cmovbe ebx,r9d
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	41 0f 46 c9          	cmovbe ecx,r9d

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.21
- Reference cycles: 9.21
- UOPS_RETIRED.ALL: 25.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.49
- UOPS_PORT_1: 7.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 9.19
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.43
- Reference cycles: 8.43
- UOPS_RETIRED.ALL: 24.11
- RETIRE_SLOTS: 24.11
- UOPS_MITE: 24.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.36
- UOPS_PORT_1: 7.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.4
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.12

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d
  20:	40                   	rex
  21:	40                   	rex
  22:	40                   	rex
  23:	40                   	rex
  24:	45 0f 46 e9          	cmovbe r13d,r9d
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	45 0f 46 f1          	cmovbe r14d,r9d
  30:	40                   	rex
  31:	40                   	rex
  32:	40                   	rex
  33:	40                   	rex
  34:	41 0f 46 d9          	cmovbe ebx,r9d
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	41 0f 46 c9          	cmovbe ecx,r9d

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.49
- Reference cycles: 8.51
- UOPS_RETIRED.ALL: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.4
- UOPS_PORT_1: 7.24
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.47
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d
  20:	41 0f 46 d1          	cmovbe edx,r9d
  24:	41 0f 46 f9          	cmovbe edi,r9d
  28:	41 0f 46 f1          	cmovbe esi,r9d
  2c:	41 0f 46 e9          	cmovbe ebp,r9d

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.53
- Reference cycles: 12.47
- UOPS_RETIRED.ALL: 36.0
- RETIRE_SLOTS: 36.0
- UOPS_MITE: 36.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.53
- UOPS_PORT_1: 10.95
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.52
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.0

With loop_count=1000 and unroll_count=1

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d
  20:	41 0f 46 d1          	cmovbe edx,r9d
  24:	41 0f 46 f9          	cmovbe edi,r9d
  28:	41 0f 46 f1          	cmovbe esi,r9d
  2c:	41 0f 46 e9          	cmovbe ebp,r9d

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 13.03
- Reference cycles: 13.04
- UOPS_RETIRED.ALL: 37.0
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 37.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.86
- UOPS_PORT_1: 11.14
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 13.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d
  20:	40                   	rex
  21:	40                   	rex
  22:	40                   	rex
  23:	40                   	rex
  24:	45 0f 46 e9          	cmovbe r13d,r9d
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	45 0f 46 f1          	cmovbe r14d,r9d
  30:	40                   	rex
  31:	40                   	rex
  32:	40                   	rex
  33:	40                   	rex
  34:	41 0f 46 d9          	cmovbe ebx,r9d
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	41 0f 46 c9          	cmovbe ecx,r9d
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	40                   	rex
  44:	41 0f 46 d1          	cmovbe edx,r9d
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	41 0f 46 f9          	cmovbe edi,r9d
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	41 0f 46 f1          	cmovbe esi,r9d
  58:	40                   	rex
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	41 0f 46 e9          	cmovbe ebp,r9d

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 13.36
- Reference cycles: 13.36
- UOPS_RETIRED.ALL: 37.0
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.71
- UOPS_PORT_1: 10.98
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 13.33
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	45 0f 46 c1          	cmovbe r8d,r9d
   4:	45 0f 46 d1          	cmovbe r10d,r9d
   8:	45 0f 46 d9          	cmovbe r11d,r9d
   c:	45 0f 46 e1          	cmovbe r12d,r9d
  10:	45 0f 46 e9          	cmovbe r13d,r9d
  14:	45 0f 46 f1          	cmovbe r14d,r9d
  18:	41 0f 46 d9          	cmovbe ebx,r9d
  1c:	41 0f 46 c9          	cmovbe ecx,r9d
  20:	41 0f 46 d1          	cmovbe edx,r9d
  24:	41 0f 46 f9          	cmovbe edi,r9d
  28:	41 0f 46 f1          	cmovbe esi,r9d
  2c:	41 0f 46 e9          	cmovbe ebp,r9d

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.61
- Reference cycles: 12.61
- UOPS_RETIRED.ALL: 36.11
- RETIRE_SLOTS: 36.11
- UOPS_MITE: 36.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.54
- UOPS_PORT_1: 10.98
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.59
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.12

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c1          	cmovbe r8d,r9d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	45 0f 46 d1          	cmovbe r10d,r9d
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	45 0f 46 d9          	cmovbe r11d,r9d
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	45 0f 46 e1          	cmovbe r12d,r9d
  20:	40                   	rex
  21:	40                   	rex
  22:	40                   	rex
  23:	40                   	rex
  24:	45 0f 46 e9          	cmovbe r13d,r9d
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	45 0f 46 f1          	cmovbe r14d,r9d
  30:	40                   	rex
  31:	40                   	rex
  32:	40                   	rex
  33:	40                   	rex
  34:	41 0f 46 d9          	cmovbe ebx,r9d
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	41 0f 46 c9          	cmovbe ecx,r9d
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	40                   	rex
  44:	41 0f 46 d1          	cmovbe edx,r9d
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	41 0f 46 f9          	cmovbe edi,r9d
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	41 0f 46 f1          	cmovbe esi,r9d
  58:	40                   	rex
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	41 0f 46 e9          	cmovbe ebp,r9d

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.68
- Reference cycles: 12.68
- UOPS_RETIRED.ALL: 36.1
- RETIRE_SLOTS: 36.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.58
- UOPS_PORT_1: 10.87
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.66
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	45 0f 46 c0          	cmovbe r8d,r8d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.97
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 0.68
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.15
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	45 0f 46 c0          	cmovbe r8d,r8d
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.2
- UOPS_PORT_1: 0.7
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	45 0f 46 c0          	cmovbe r8d,r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 2.0
- UOPS_RETIRED.ALL: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 0.68
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.25
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.1

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c0          	cmovbe r8d,r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 2.0
- UOPS_RETIRED.ALL: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 0.68
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.25
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	45 0f 46 c0          	cmovbe r8d,r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 2.0
- UOPS_RETIRED.ALL: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.16
- UOPS_PORT_1: 0.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.18
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	45 0f 46 c0          	cmovbe r8d,r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 2.0
- UOPS_RETIRED.ALL: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.16
- UOPS_PORT_1: 0.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.18
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

CMOVBE (R32, R32) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With the same register for for different operands

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)