BSR (R64, M64) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 3.01
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_RETIRED.ALL: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_RETIRED.ALL: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.06
- Reference cycles: 4.05
- UOPS_RETIRED.ALL: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.06
- Reference cycles: 4.07
- UOPS_RETIRED.ALL: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 4.06
- UOPS_RETIRED.ALL: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.05
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]
  13:	4d 0f bd 66 20       	bsr    r12,QWORD PTR [r14+0x20]
  18:	49 0f bd 5e 28       	bsr    rbx,QWORD PTR [r14+0x28]
  1d:	49 0f bd 4e 30       	bsr    rcx,QWORD PTR [r14+0x30]
  22:	49 0f bd 56 38       	bsr    rdx,QWORD PTR [r14+0x38]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.11
- Reference cycles: 7.99
- UOPS_RETIRED.ALL: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]
  13:	4d 0f bd 66 20       	bsr    r12,QWORD PTR [r14+0x20]
  18:	49 0f bd 5e 28       	bsr    rbx,QWORD PTR [r14+0x28]
  1d:	49 0f bd 4e 30       	bsr    rcx,QWORD PTR [r14+0x30]
  22:	49 0f bd 56 38       	bsr    rdx,QWORD PTR [r14+0x38]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.13
- Reference cycles: 8.12
- UOPS_RETIRED.ALL: 17.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f bd 4e 08       	bsr    r9,QWORD PTR [r14+0x8]
   9:	4d 0f bd 56 10       	bsr    r10,QWORD PTR [r14+0x10]
   e:	4d 0f bd 5e 18       	bsr    r11,QWORD PTR [r14+0x18]
  13:	4d 0f bd 66 20       	bsr    r12,QWORD PTR [r14+0x20]
  18:	49 0f bd 5e 28       	bsr    rbx,QWORD PTR [r14+0x28]
  1d:	49 0f bd 4e 30       	bsr    rcx,QWORD PTR [r14+0x30]
  22:	49 0f bd 56 38       	bsr    rdx,QWORD PTR [r14+0x38]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 8.13
- UOPS_RETIRED.ALL: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_RETIRED.ALL: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_RETIRED.ALL: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.06
- Reference cycles: 4.05
- UOPS_RETIRED.ALL: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.06
- Reference cycles: 4.06
- UOPS_RETIRED.ALL: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 4.06
- UOPS_RETIRED.ALL: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.05
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]
  17:	4f 0f bd 64 2e 20    	bsr    r12,QWORD PTR [r14+r13*1+0x20]
  1d:	4b 0f bd 5c 2e 28    	bsr    rbx,QWORD PTR [r14+r13*1+0x28]
  23:	4b 0f bd 4c 2e 30    	bsr    rcx,QWORD PTR [r14+r13*1+0x30]
  29:	4b 0f bd 54 2e 38    	bsr    rdx,QWORD PTR [r14+r13*1+0x38]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.11
- Reference cycles: 7.99
- UOPS_RETIRED.ALL: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]
  17:	4f 0f bd 64 2e 20    	bsr    r12,QWORD PTR [r14+r13*1+0x20]
  1d:	4b 0f bd 5c 2e 28    	bsr    rbx,QWORD PTR [r14+r13*1+0x28]
  23:	4b 0f bd 4c 2e 30    	bsr    rcx,QWORD PTR [r14+r13*1+0x30]
  29:	4b 0f bd 54 2e 38    	bsr    rdx,QWORD PTR [r14+r13*1+0x38]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.13
- Reference cycles: 8.13
- UOPS_RETIRED.ALL: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4f 0f bd 4c 2e 08    	bsr    r9,QWORD PTR [r14+r13*1+0x8]
   b:	4f 0f bd 54 2e 10    	bsr    r10,QWORD PTR [r14+r13*1+0x10]
  11:	4f 0f bd 5c 2e 18    	bsr    r11,QWORD PTR [r14+r13*1+0x18]
  17:	4f 0f bd 64 2e 20    	bsr    r12,QWORD PTR [r14+r13*1+0x20]
  1d:	4b 0f bd 5c 2e 28    	bsr    rbx,QWORD PTR [r14+r13*1+0x28]
  23:	4b 0f bd 4c 2e 30    	bsr    rcx,QWORD PTR [r14+r13*1+0x30]
  29:	4b 0f bd 54 2e 38    	bsr    rdx,QWORD PTR [r14+r13*1+0x38]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 8.14
- UOPS_RETIRED.ALL: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

Tests for macro-fusion

With JB (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 82 00 00 00 00    	jb     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JB (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	72 00                	jb     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JBE (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 86 00 00 00 00    	jbe    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JBE (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	76 00                	jbe    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JL (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8c 00 00 00 00    	jl     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JL (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7c 00                	jl     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.29
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JLE (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8e 00 00 00 00    	jle    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JLE (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7e 00                	jle    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNB (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 83 00 00 00 00    	jae    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.35
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNB (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	73 00                	jae    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.04
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.96
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.49

With JNBE (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 87 00 00 00 00    	ja     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.42
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNBE (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	77 00                	ja     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.95
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With JNL (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8d 00 00 00 00    	jge    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.09
- Reference cycles: 3.23
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.35
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNL (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7d 00                	jge    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.23
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.93
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With JNLE (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8f 00 00 00 00    	jg     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With JNLE (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7f 00                	jg     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With JNO (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 81 00 00 00 00    	jno    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.09
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNO (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	71 00                	jno    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.51

With JNP (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8b 00 00 00 00    	jnp    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.09
- Reference cycles: 3.06
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNP (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7b 00                	jnp    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.85
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With JNS (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 89 00 00 00 00    	jns    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.29
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.3
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNS (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	79 00                	jns    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.95
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.51

With JNZ (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 85 00 00 00 00    	jne    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.31
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNZ (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	75 00                	jne    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 0.51
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With JO (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 80 00 00 00 00    	jo     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JO (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	70 00                	jo     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.06
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JP (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 8a 00 00 00 00    	jp     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JP (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	7a 00                	jp     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.49
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JS (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 88 00 00 00 00    	js     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JS (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	78 00                	js     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.17
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JZ (Rel32)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	0f 84 00 00 00 00    	je     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JZ (Rel8)

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	74 00                	je     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.12
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02