ADDSD (XMM, M64) - Throughput and Uops (IACA 2.3)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 2.86 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm0, qword ptr [r14]
Total Num Of Uops: 2
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 13.00 Cycles Throughput Bottleneck: Backend. Port1
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 13.0 | 6.5 6.5 | 6.5 6.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm0, qword ptr [r14]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm1, qword ptr [r14+0x8]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm2, qword ptr [r14+0x10]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm3, qword ptr [r14+0x18]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm4, qword ptr [r14+0x20]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm5, qword ptr [r14+0x28]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm6, qword ptr [r14+0x30]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm7, qword ptr [r14+0x38]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm8, qword ptr [r14+0x40]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm9, qword ptr [r14+0x48]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm10, qword ptr [r14+0x50]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm11, qword ptr [r14+0x58]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm12, qword ptr [r14+0x60]
Total Num Of Uops: 26
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 2.86 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm0, qword ptr [r14+r13*1]
Total Num Of Uops: 2
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 13.00 Cycles Throughput Bottleneck: Backend. Port1
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 13.0 | 6.5 6.5 | 6.5 6.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm0, qword ptr [r14+r13*1]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm1, qword ptr [r14+r13*1+0x8]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm2, qword ptr [r14+r13*1+0x10]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm3, qword ptr [r14+r13*1+0x18]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm4, qword ptr [r14+r13*1+0x20]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm5, qword ptr [r14+r13*1+0x28]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm6, qword ptr [r14+r13*1+0x30]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm7, qword ptr [r14+r13*1+0x38]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm8, qword ptr [r14+r13*1+0x40]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm9, qword ptr [r14+r13*1+0x48]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm10, qword ptr [r14+r13*1+0x50]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm11, qword ptr [r14+r13*1+0x58]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | CP | addsd xmm12, qword ptr [r14+r13*1+0x60]
Total Num Of Uops: 26