ADC (RAX, I32) - Throughput and Uops (IACA 2.3)

Throughput Analysis Report
--------------------------
Block Throughput: 1.90 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.6    0.0  | 0.7  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.6  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    | 0.6       | 0.7 |           |           |     | 0.6 | CP | adc rax, 0x1000000
Total Num Of Uops: 2

With additional dependency-breaking instructions

Throughput Analysis Report
--------------------------
Block Throughput: 0.71 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.6    0.0  | 0.7  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.6  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    | 0.6       | 0.7 |           |           |     | 0.6 | CP | adc rax, 0x1000000
|   1*   |           |     |           |           |     |     |    | xor rax, rax
Total Num Of Uops: 3