ADC (R64, 0) - Throughput and Uops

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.52
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.48
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.44
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.97
- UOPS_RETIRED.ALL: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_RETIRED.ALL: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.6
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_RETIRED.ALL: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.47
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_RETIRED.ALL: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.49
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.62
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_RETIRED.ALL: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.49
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_RETIRED.ALL: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.07
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.93
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_RETIRED.ALL: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 4.01
- UOPS_RETIRED.ALL: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.02
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.94
- UOPS_RETIRED.ALL: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.0
- UOPS_PORT_1: 2.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 3.2
- Reference cycles: 3.21
- UOPS_RETIRED.ALL: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.71
- UOPS_PORT_1: 2.62
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.18
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0

Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 2.8
- Reference cycles: 2.81
- UOPS_RETIRED.ALL: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.68
- UOPS_PORT_1: 2.6
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.78
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.93
- UOPS_RETIRED.ALL: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.14
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.86
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.02
- UOPS_RETIRED.ALL: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 8.02
- UOPS_RETIRED.ALL: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.04
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.06
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 7.88
- UOPS_RETIRED.ALL: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 5.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 6.35
- Reference cycles: 6.35
- UOPS_RETIRED.ALL: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.44
- UOPS_PORT_1: 5.25
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.32
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 5.59
- Reference cycles: 5.6
- UOPS_RETIRED.ALL: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.38
- UOPS_PORT_1: 5.2
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.53
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0
  20:	48 83 d1 00          	adc    rcx,0x0
  24:	48 83 d2 00          	adc    rdx,0x0
  28:	48 83 d7 00          	adc    rdi,0x0
  2c:	48 83 d6 00          	adc    rsi,0x0
  30:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.0
- Reference cycles: 12.98
- UOPS_RETIRED.ALL: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.73
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.27
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0
  20:	48 83 d1 00          	adc    rcx,0x0
  24:	48 83 d2 00          	adc    rdx,0x0
  28:	48 83 d7 00          	adc    rdi,0x0
  2c:	48 83 d6 00          	adc    rsi,0x0
  30:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 13.01
- Reference cycles: 13.02
- UOPS_RETIRED.ALL: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.59
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.41
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	49 83 d1 00          	adc    r9,0x0
   8:	49 83 d2 00          	adc    r10,0x0
   c:	49 83 d3 00          	adc    r11,0x0
  10:	49 83 d4 00          	adc    r12,0x0
  14:	49 83 d5 00          	adc    r13,0x0
  18:	49 83 d6 00          	adc    r14,0x0
  1c:	48 83 d3 00          	adc    rbx,0x0
  20:	48 83 d1 00          	adc    rcx,0x0
  24:	48 83 d2 00          	adc    rdx,0x0
  28:	48 83 d7 00          	adc    rdi,0x0
  2c:	48 83 d6 00          	adc    rsi,0x0
  30:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 13.01
- Reference cycles: 13.02
- UOPS_RETIRED.ALL: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.55
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0
  38:	4d 85 ff             	test   r15,r15
  3b:	48 83 d1 00          	adc    rcx,0x0
  3f:	4d 85 ff             	test   r15,r15
  42:	48 83 d2 00          	adc    rdx,0x0
  46:	4d 85 ff             	test   r15,r15
  49:	48 83 d7 00          	adc    rdi,0x0
  4d:	4d 85 ff             	test   r15,r15
  50:	48 83 d6 00          	adc    rsi,0x0
  54:	4d 85 ff             	test   r15,r15
  57:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 26.0
- Core cycles: 13.14
- Reference cycles: 13.03
- UOPS_RETIRED.ALL: 26.0
- RETIRE_SLOTS: 26.0
- UOPS_MITE: 26.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.76
- UOPS_PORT_1: 8.11
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.13
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.03

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0
  38:	4d 85 ff             	test   r15,r15
  3b:	48 83 d1 00          	adc    rcx,0x0
  3f:	4d 85 ff             	test   r15,r15
  42:	48 83 d2 00          	adc    rdx,0x0
  46:	4d 85 ff             	test   r15,r15
  49:	48 83 d7 00          	adc    rdi,0x0
  4d:	4d 85 ff             	test   r15,r15
  50:	48 83 d6 00          	adc    rsi,0x0
  54:	4d 85 ff             	test   r15,r15
  57:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 28.0
- Core cycles: 9.05
- Reference cycles: 9.06
- UOPS_RETIRED.ALL: 27.0
- RETIRE_SLOTS: 27.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.0
- UOPS_PORT_1: 8.98
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 9.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	4d 85 ff             	test   r15,r15
   3:	49 83 d0 00          	adc    r8,0x0
   7:	4d 85 ff             	test   r15,r15
   a:	49 83 d1 00          	adc    r9,0x0
   e:	4d 85 ff             	test   r15,r15
  11:	49 83 d2 00          	adc    r10,0x0
  15:	4d 85 ff             	test   r15,r15
  18:	49 83 d3 00          	adc    r11,0x0
  1c:	4d 85 ff             	test   r15,r15
  1f:	49 83 d4 00          	adc    r12,0x0
  23:	4d 85 ff             	test   r15,r15
  26:	49 83 d5 00          	adc    r13,0x0
  2a:	4d 85 ff             	test   r15,r15
  2d:	49 83 d6 00          	adc    r14,0x0
  31:	4d 85 ff             	test   r15,r15
  34:	48 83 d3 00          	adc    rbx,0x0
  38:	4d 85 ff             	test   r15,r15
  3b:	48 83 d1 00          	adc    rcx,0x0
  3f:	4d 85 ff             	test   r15,r15
  42:	48 83 d2 00          	adc    rdx,0x0
  46:	4d 85 ff             	test   r15,r15
  49:	48 83 d7 00          	adc    rdi,0x0
  4d:	4d 85 ff             	test   r15,r15
  50:	48 83 d6 00          	adc    rsi,0x0
  54:	4d 85 ff             	test   r15,r15
  57:	48 83 d5 00          	adc    rbp,0x0

Show nanoBench command
Results:
- Instructions retired: 26.2
- Core cycles: 8.94
- Reference cycles: 8.94
- UOPS_RETIRED.ALL: 26.1
- RETIRE_SLOTS: 26.1
- UOPS_MITE: 0.26
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.7
- UOPS_PORT_1: 8.52
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.9
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

Tests for macro-fusion

With JB (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 82 00 00 00 00    	jb     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.3
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JB (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	72 00                	jb     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JBE (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 86 00 00 00 00    	jbe    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.95
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.22
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.39

With JBE (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	76 00                	jbe    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.94
- Reference cycles: 2.04
- UOPS_RETIRED.ALL: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.78
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.53

With JL (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8c 00 00 00 00    	jl     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.08
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JL (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7c 00                	jl     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.08
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JLE (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8e 00 00 00 00    	jle    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.97
- Reference cycles: 2.04
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With JLE (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7e 00                	jle    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.15
- Reference cycles: 2.32
- UOPS_RETIRED.ALL: 2.02
- RETIRE_SLOTS: 2.02
- UOPS_MITE: 0.71
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.39

With JNB (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 83 00 00 00 00    	jae    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.95
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.37
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.23

With JNB (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	73 00                	jae    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.77
- Reference cycles: 1.87
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.96
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.55

With JNBE (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 87 00 00 00 00    	ja     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 1.3
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNBE (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	77 00                	ja     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.19
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNL (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8d 00 00 00 00    	jge    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.95
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.41
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.26

With JNL (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7d 00                	jge    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.79
- Reference cycles: 1.64
- UOPS_RETIRED.ALL: 2.04
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.89
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.58

With JNLE (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8f 00 00 00 00    	jg     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.15
- Reference cycles: 1.3
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNLE (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7f 00                	jg     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.14
- Reference cycles: 1.19
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNO (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 81 00 00 00 00    	jno    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.98
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.27
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNO (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	71 00                	jno    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.81
- Reference cycles: 1.7
- UOPS_RETIRED.ALL: 2.04
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.58

With JNP (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8b 00 00 00 00    	jnp    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 1.08
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNP (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7b 00                	jnp    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.11
- Reference cycles: 1.25
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNS (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 89 00 00 00 00    	jns    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.96
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.34
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With JNS (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	79 00                	jns    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.81
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.86
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.56

With JNZ (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 85 00 00 00 00    	jne    0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.19
- Reference cycles: 1.3
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JNZ (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	75 00                	jne    0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.14
- Reference cycles: 1.25
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.92
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JO (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 80 00 00 00 00    	jo     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.25
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JO (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	70 00                	jo     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.13
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JP (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 8a 00 00 00 00    	jp     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.97
- Reference cycles: 1.93
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.33

With JP (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	7a 00                	jp     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.01
- Reference cycles: 2.1
- UOPS_RETIRED.ALL: 2.03
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 0.66
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.46

With JS (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 88 00 00 00 00    	js     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.13
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JS (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	78 00                	js     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.09
- Reference cycles: 1.25
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With JZ (Rel32)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	0f 84 00 00 00 00    	je     0xa

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.95
- Reference cycles: 1.98
- UOPS_RETIRED.ALL: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.31

With JZ (Rel8)

Code:

   0:	49 83 d0 00          	adc    r8,0x0
   4:	74 00                	je     0x6

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.08
- Reference cycles: 2.15
- UOPS_RETIRED.ALL: 2.03
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 0.72
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.51