VPMULLQ (YMM, K, YMM, YMM) - Throughput and Uops (IACA 3.0)


With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 11.66 Cycles       Throughput Bottleneck: Backend
Loop Count:  38
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  1.0     0.0  |  1.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  1.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm0{k1}, ymm1, ymm2
Total Num Of Uops: 3

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 15.95 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles | 16.0     0.0  | 16.0  |  0.0     0.0  |  0.0     0.0  |  0.0  | 16.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm0{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm3{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm4{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm5{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm6{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm7{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm8{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm9{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm10{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm11{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm12{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm16{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm17{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm18{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm19{k1}, ymm1, ymm2
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm20{k1}, ymm1, ymm2
Total Num Of Uops: 48

With the same register for for different operands

Throughput Analysis Report
--------------------------
Block Throughput: 11.66 Cycles       Throughput Bottleneck: Backend
Loop Count:  38
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  1.0     0.0  |  1.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  1.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 1.0         | 1.0  |             |             |      | 1.0  |      |      | vpmullq ymm0{k1}, ymm0, ymm0
Total Num Of Uops: 3