VPMULLQ (YMM, K, YMM, YMM) - Throughput and Uops (IACA 2.3)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
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Block Throughput: 11.43 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
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| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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| Cycles | 1.0 0.0 | 1.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
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| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm0{k1}, ymm1, ymm2
Total Num Of Uops: 3
With 16 independent instructions
Throughput Analysis Report
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Block Throughput: 16.00 Cycles Throughput Bottleneck: Backend. Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
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| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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| Cycles | 16.0 0.0 | 16.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 16.0 | 0.0 | 0.0 |
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| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm0{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm3{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm4{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm5{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm6{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm7{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm8{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm9{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm10{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm11{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm12{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm16{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm17{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm18{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm19{k1}, ymm1, ymm2
| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm20{k1}, ymm1, ymm2
Total Num Of Uops: 48
With the same register for for different operands
Throughput Analysis Report
--------------------------
Block Throughput: 11.43 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 3 | 1.0 | 1.0 | | | | 1.0 | | | CP | vpmullq ymm0{k1}, ymm0, ymm0
Total Num Of Uops: 3