VPCMPEQW (K, ZMM, ZMM) - Throughput and Uops (IACA 2.3)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 1.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k1, zmm0, zmm1
Total Num Of Uops: 1

With 7 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 7.00 Cycles       Throughput Bottleneck: Backend. Port5

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 7.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k1, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k2, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k3, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k4, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k5, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k6, zmm0, zmm1
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k7, zmm0, zmm1
Total Num Of Uops: 7

With the same register for for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 1.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k1, zmm0, zmm0
Total Num Of Uops: 1

With 7 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 7.00 Cycles       Throughput Bottleneck: Backend. Port5

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 7.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k1, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k2, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k3, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k4, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k5, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k6, zmm0, zmm0
|   1    |           |     |           |           |     | 1.0 |     |     | CP | vpcmpeqw k7, zmm0, zmm0
Total Num Of Uops: 7