VPCMPB (K, ZMM, M512, I8)

With unroll_count=500 and no inner loop

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.19
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.89
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 8.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02 
  1f:	62 d3 7d 48 3f 6e 04 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+0x100]
  26:	02 
  27:	62 d3 7d 48 3f 76 05 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+0x140]
  2e:	02 
  2f:	62 d3 7d 48 3f 7e 06 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+0x180]
  36:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 14.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02 
  1f:	62 d3 7d 48 3f 6e 04 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+0x100]
  26:	02 
  27:	62 d3 7d 48 3f 76 05 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+0x140]
  2e:	02 
  2f:	62 d3 7d 48 3f 7e 06 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+0x180]
  36:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.02
- Reference cycles: 6.67
- UOPS_EXECUTED.THREAD: 15.0
- RETIRE_SLOTS: 15.0
- UOPS_MITE: 15.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d3 7d 48 3f 0e 02 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14]
   7:	62 d3 7d 48 3f 56 01 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+0x40]
   e:	02 
   f:	62 d3 7d 48 3f 5e 02 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+0x80]
  16:	02 
  17:	62 d3 7d 48 3f 66 03 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  1e:	02 
  1f:	62 d3 7d 48 3f 6e 04 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+0x100]
  26:	02 
  27:	62 d3 7d 48 3f 76 05 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+0x140]
  2e:	02 
  2f:	62 d3 7d 48 3f 7e 06 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+0x180]
  36:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.02
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 14.11
- RETIRE_SLOTS: 14.1
- UOPS_MITE: 0.14
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.92
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.77
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.03
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.72
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02 
  23:	62 93 7d 48 3f 6c 2e 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
  2a:	04 02 
  2c:	62 93 7d 48 3f 74 2e 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
  33:	05 02 
  35:	62 93 7d 48 3f 7c 2e 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
  3c:	06 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 14.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02 
  23:	62 93 7d 48 3f 6c 2e 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
  2a:	04 02 
  2c:	62 93 7d 48 3f 74 2e 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
  33:	05 02 
  35:	62 93 7d 48 3f 7c 2e 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
  3c:	06 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.02
- Reference cycles: 6.64
- UOPS_EXECUTED.THREAD: 15.0
- RETIRE_SLOTS: 15.0
- UOPS_MITE: 15.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 93 7d 48 3f 0c 2e 	vpcmpleb k1,zmm0,ZMMWORD PTR [r14+r13*1]
   7:	02 
   8:	62 93 7d 48 3f 54 2e 	vpcmpleb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
   f:	01 02 
  11:	62 93 7d 48 3f 5c 2e 	vpcmpleb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
  18:	02 02 
  1a:	62 93 7d 48 3f 64 2e 	vpcmpleb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
  21:	03 02 
  23:	62 93 7d 48 3f 6c 2e 	vpcmpleb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
  2a:	04 02 
  2c:	62 93 7d 48 3f 74 2e 	vpcmpleb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
  33:	05 02 
  35:	62 93 7d 48 3f 7c 2e 	vpcmpleb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
  3c:	06 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.02
- Reference cycles: 7.01
- UOPS_EXECUTED.THREAD: 14.11
- RETIRE_SLOTS: 14.1
- UOPS_MITE: 0.14
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

VPCMPB (K, ZMM, M512, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10