VMOVDQU8 (M128, K, XMM) - Throughput and Uops (IACA 3.0)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.92 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 68
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 0.0 | 0.3 0.0 | 0.3 0.0 | 1.0 | 0.0 | 0.0 | 0.3 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14]{k1}, xmm0
Total Num Of Uops: 2
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 0.0 | 5.3 0.0 | 5.4 0.0 | 16.0 | 0.0 | 0.0 | 5.3 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14]{k1}, xmm0
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.4 | vmovdqu8 xmmword ptr [r14+0x10]{k1}, xmm0
| 2^ | | | 0.4 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x20]{k1}, xmm0
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x30]{k1}, xmm0
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.4 | vmovdqu8 xmmword ptr [r14+0x40]{k1}, xmm0
| 2^ | | | 0.4 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x50]{k1}, xmm0
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x60]{k1}, xmm0
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.4 | vmovdqu8 xmmword ptr [r14+0x70]{k1}, xmm0
| 2^ | | | 0.4 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x80]{k1}, xmm0
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0x90]{k1}, xmm0
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.4 | vmovdqu8 xmmword ptr [r14+0xa0]{k1}, xmm0
| 2^ | | | 0.4 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0xb0]{k1}, xmm0
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0xc0]{k1}, xmm0
| 2^ | | | 0.3 | 0.3 | 1.0 | | | 0.4 | vmovdqu8 xmmword ptr [r14+0xd0]{k1}, xmm0
| 2^ | | | 0.4 | 0.3 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0xe0]{k1}, xmm0
| 2^ | | | 0.3 | 0.4 | 1.0 | | | 0.3 | vmovdqu8 xmmword ptr [r14+0xf0]{k1}, xmm0
Total Num Of Uops: 32
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.84 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 34
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 0.0 | 0.5 0.0 | 0.5 0.0 | 1.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | | | 0.5 | 0.5 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1]{k1}, xmm0
Total Num Of Uops: 2
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 0.0 | 8.0 0.0 | 8.0 0.0 | 16.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x10]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x20]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x30]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x40]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x50]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x60]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x70]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x80]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0x90]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xa0]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xb0]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xc0]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xd0]{k1}, xmm0
| 2 | | | 1.0 | | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xe0]{k1}, xmm0
| 2 | | | | 1.0 | 1.0 | | | | vmovdqu8 xmmword ptr [r14+r13*1+0xf0]{k1}, xmm0
Total Num Of Uops: 32