VMOVDQA (M256, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.02
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.33
- UOPS_PORT_3: 0.33
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.34
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.3
- UOPS_PORT_3: 0.35
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.92
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.33
- UOPS_PORT_3: 0.33
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.33
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.34
- UOPS_PORT_3: 1.33
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 1.33
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.63
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.25
- UOPS_PORT_3: 1.42
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 1.36
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.71
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.32
- UOPS_PORT_3: 1.34
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 1.34
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.67
- UOPS_PORT_3: 2.67
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 2.66
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 7.18
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.5
- UOPS_PORT_3: 2.79
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 2.75
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.02

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 7.23
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.65
- UOPS_PORT_3: 2.68
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 2.68
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00 
  3b:	c4 c1 7d 7f 86 00 01 	vmovdqa YMMWORD PTR [r14+0x100],ymm0
  42:	00 00 
  44:	c4 c1 7d 7f 86 20 01 	vmovdqa YMMWORD PTR [r14+0x120],ymm0
  4b:	00 00 
  4d:	c4 c1 7d 7f 86 40 01 	vmovdqa YMMWORD PTR [r14+0x140],ymm0
  54:	00 00 
  56:	c4 c1 7d 7f 86 60 01 	vmovdqa YMMWORD PTR [r14+0x160],ymm0
  5d:	00 00 
  5f:	c4 c1 7d 7f 86 80 01 	vmovdqa YMMWORD PTR [r14+0x180],ymm0
  66:	00 00 
  68:	c4 c1 7d 7f 86 a0 01 	vmovdqa YMMWORD PTR [r14+0x1a0],ymm0
  6f:	00 00 
  71:	c4 c1 7d 7f 86 c0 01 	vmovdqa YMMWORD PTR [r14+0x1c0],ymm0
  78:	00 00 
  7a:	c4 c1 7d 7f 86 e0 01 	vmovdqa YMMWORD PTR [r14+0x1e0],ymm0
  81:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 14.11
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 5.33
- UOPS_PORT_3: 5.34
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 5.34
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00 
  3b:	c4 c1 7d 7f 86 00 01 	vmovdqa YMMWORD PTR [r14+0x100],ymm0
  42:	00 00 
  44:	c4 c1 7d 7f 86 20 01 	vmovdqa YMMWORD PTR [r14+0x120],ymm0
  4b:	00 00 
  4d:	c4 c1 7d 7f 86 40 01 	vmovdqa YMMWORD PTR [r14+0x140],ymm0
  54:	00 00 
  56:	c4 c1 7d 7f 86 60 01 	vmovdqa YMMWORD PTR [r14+0x160],ymm0
  5d:	00 00 
  5f:	c4 c1 7d 7f 86 80 01 	vmovdqa YMMWORD PTR [r14+0x180],ymm0
  66:	00 00 
  68:	c4 c1 7d 7f 86 a0 01 	vmovdqa YMMWORD PTR [r14+0x1a0],ymm0
  6f:	00 00 
  71:	c4 c1 7d 7f 86 c0 01 	vmovdqa YMMWORD PTR [r14+0x1c0],ymm0
  78:	00 00 
  7a:	c4 c1 7d 7f 86 e0 01 	vmovdqa YMMWORD PTR [r14+0x1e0],ymm0
  81:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 14.41
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 5.13
- UOPS_PORT_3: 5.38
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 5.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 c1 7d 7f 46 20    	vmovdqa YMMWORD PTR [r14+0x20],ymm0
   b:	c4 c1 7d 7f 46 40    	vmovdqa YMMWORD PTR [r14+0x40],ymm0
  11:	c4 c1 7d 7f 46 60    	vmovdqa YMMWORD PTR [r14+0x60],ymm0
  17:	c4 c1 7d 7f 86 80 00 	vmovdqa YMMWORD PTR [r14+0x80],ymm0
  1e:	00 00 
  20:	c4 c1 7d 7f 86 a0 00 	vmovdqa YMMWORD PTR [r14+0xa0],ymm0
  27:	00 00 
  29:	c4 c1 7d 7f 86 c0 00 	vmovdqa YMMWORD PTR [r14+0xc0],ymm0
  30:	00 00 
  32:	c4 c1 7d 7f 86 e0 00 	vmovdqa YMMWORD PTR [r14+0xe0],ymm0
  39:	00 00 
  3b:	c4 c1 7d 7f 86 00 01 	vmovdqa YMMWORD PTR [r14+0x100],ymm0
  42:	00 00 
  44:	c4 c1 7d 7f 86 20 01 	vmovdqa YMMWORD PTR [r14+0x120],ymm0
  4b:	00 00 
  4d:	c4 c1 7d 7f 86 40 01 	vmovdqa YMMWORD PTR [r14+0x140],ymm0
  54:	00 00 
  56:	c4 c1 7d 7f 86 60 01 	vmovdqa YMMWORD PTR [r14+0x160],ymm0
  5d:	00 00 
  5f:	c4 c1 7d 7f 86 80 01 	vmovdqa YMMWORD PTR [r14+0x180],ymm0
  66:	00 00 
  68:	c4 c1 7d 7f 86 a0 01 	vmovdqa YMMWORD PTR [r14+0x1a0],ymm0
  6f:	00 00 
  71:	c4 c1 7d 7f 86 c0 01 	vmovdqa YMMWORD PTR [r14+0x1c0],ymm0
  78:	00 00 
  7a:	c4 c1 7d 7f 86 e0 01 	vmovdqa YMMWORD PTR [r14+0x1e0],ymm0
  81:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 14.38
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.56
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 5.31
- UOPS_PORT_3: 5.34
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 5.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.15

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.6
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.6
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.11

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 7.2
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 7.23
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00 
  43:	c4 81 7d 7f 84 2e 00 	vmovdqa YMMWORD PTR [r14+r13*1+0x100],ymm0
  4a:	01 00 00 
  4d:	c4 81 7d 7f 84 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x120],ymm0
  54:	01 00 00 
  57:	c4 81 7d 7f 84 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x140],ymm0
  5e:	01 00 00 
  61:	c4 81 7d 7f 84 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x160],ymm0
  68:	01 00 00 
  6b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x180],ymm0
  72:	01 00 00 
  75:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1a0],ymm0
  7c:	01 00 00 
  7f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1c0],ymm0
  86:	01 00 00 
  89:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1e0],ymm0
  90:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 14.6
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00 
  43:	c4 81 7d 7f 84 2e 00 	vmovdqa YMMWORD PTR [r14+r13*1+0x100],ymm0
  4a:	01 00 00 
  4d:	c4 81 7d 7f 84 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x120],ymm0
  54:	01 00 00 
  57:	c4 81 7d 7f 84 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x140],ymm0
  5e:	01 00 00 
  61:	c4 81 7d 7f 84 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x160],ymm0
  68:	01 00 00 
  6b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x180],ymm0
  72:	01 00 00 
  75:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1a0],ymm0
  7c:	01 00 00 
  7f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1c0],ymm0
  86:	01 00 00 
  89:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1e0],ymm0
  90:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 14.43
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	c4 81 7d 7f 44 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x20],ymm0
   d:	c4 81 7d 7f 44 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x40],ymm0
  14:	c4 81 7d 7f 44 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x60],ymm0
  1b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x80],ymm0
  22:	00 00 00 
  25:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0xa0],ymm0
  2c:	00 00 00 
  2f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0xc0],ymm0
  36:	00 00 00 
  39:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0xe0],ymm0
  40:	00 00 00 
  43:	c4 81 7d 7f 84 2e 00 	vmovdqa YMMWORD PTR [r14+r13*1+0x100],ymm0
  4a:	01 00 00 
  4d:	c4 81 7d 7f 84 2e 20 	vmovdqa YMMWORD PTR [r14+r13*1+0x120],ymm0
  54:	01 00 00 
  57:	c4 81 7d 7f 84 2e 40 	vmovdqa YMMWORD PTR [r14+r13*1+0x140],ymm0
  5e:	01 00 00 
  61:	c4 81 7d 7f 84 2e 60 	vmovdqa YMMWORD PTR [r14+r13*1+0x160],ymm0
  68:	01 00 00 
  6b:	c4 81 7d 7f 84 2e 80 	vmovdqa YMMWORD PTR [r14+r13*1+0x180],ymm0
  72:	01 00 00 
  75:	c4 81 7d 7f 84 2e a0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1a0],ymm0
  7c:	01 00 00 
  7f:	c4 81 7d 7f 84 2e c0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1c0],ymm0
  86:	01 00 00 
  89:	c4 81 7d 7f 84 2e e0 	vmovdqa YMMWORD PTR [r14+r13*1+0x1e0],ymm0
  90:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 14.41
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.85
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

VMOVDQA (M256, YMM) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10