VMOVDQA64 (YMM, K, M256) - Throughput and Uops (IACA 2.3)


With a non-indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.95 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.3    0.0  | 0.3  | 0.5    0.5  | 0.5    0.5  | 0.0  | 0.3  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    | 0.3       | 0.3 | 0.5   0.5 | 0.5   0.5 |     | 0.3 |     |     | CP | vmovdqa64 ymm0{k1}, ymmword ptr [r14]
Total Num Of Uops: 2

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 8.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 5.3    0.0  | 5.3  | 8.0    8.0  | 8.0    8.0  | 0.0  | 5.3  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm0{k1}, ymmword ptr [r14]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm1{k1}, ymmword ptr [r14+0x20]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm2{k1}, ymmword ptr [r14+0x40]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm3{k1}, ymmword ptr [r14+0x60]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm4{k1}, ymmword ptr [r14+0x80]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm5{k1}, ymmword ptr [r14+0xa0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm6{k1}, ymmword ptr [r14+0xc0]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm7{k1}, ymmword ptr [r14+0xe0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm8{k1}, ymmword ptr [r14+0x100]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm9{k1}, ymmword ptr [r14+0x120]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm10{k1}, ymmword ptr [r14+0x140]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm11{k1}, ymmword ptr [r14+0x160]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm12{k1}, ymmword ptr [r14+0x180]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm16{k1}, ymmword ptr [r14+0x1a0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm17{k1}, ymmword ptr [r14+0x1c0]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm18{k1}, ymmword ptr [r14+0x1e0]
Total Num Of Uops: 32

With an indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.95 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.3    0.0  | 0.3  | 0.5    0.5  | 0.5    0.5  | 0.0  | 0.3  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    | 0.3       | 0.3 | 0.5   0.5 | 0.5   0.5 |     | 0.3 |     |     | CP | vmovdqa64 ymm0{k1}, ymmword ptr [r14+r13*1]
Total Num Of Uops: 2

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 8.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 5.3    0.0  | 5.3  | 8.0    8.0  | 8.0    8.0  | 0.0  | 5.3  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm0{k1}, ymmword ptr [r14+r13*1]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm1{k1}, ymmword ptr [r14+r13*1+0x20]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm2{k1}, ymmword ptr [r14+r13*1+0x40]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm3{k1}, ymmword ptr [r14+r13*1+0x60]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm4{k1}, ymmword ptr [r14+r13*1+0x80]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm5{k1}, ymmword ptr [r14+r13*1+0xa0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm6{k1}, ymmword ptr [r14+r13*1+0xc0]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm7{k1}, ymmword ptr [r14+r13*1+0xe0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm8{k1}, ymmword ptr [r14+r13*1+0x100]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm9{k1}, ymmword ptr [r14+r13*1+0x120]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm10{k1}, ymmword ptr [r14+r13*1+0x140]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm11{k1}, ymmword ptr [r14+r13*1+0x160]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm12{k1}, ymmword ptr [r14+r13*1+0x180]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm16{k1}, ymmword ptr [r14+r13*1+0x1a0]
|   2    | 0.3       | 0.3 | 1.0   1.0 |           |     | 0.3 |     |     | CP | vmovdqa64 ymm17{k1}, ymmword ptr [r14+r13*1+0x1c0]
|   2    | 0.3       | 0.3 |           | 1.0   1.0 |     | 0.3 |     |     | CP | vmovdqa64 ymm18{k1}, ymmword ptr [r14+r13*1+0x1e0]
Total Num Of Uops: 32