VINSERTI32X4 (ZMM, ZMM, M128, I8)

With unroll_count=500 and no inner loop

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.62
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.62
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.61
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.39
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.71
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.29
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.53
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.48
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 0.8
- Reference cycles: 0.76
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.4
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.52
- Reference cycles: 0.49
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.19
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.51
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.49
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 0.76
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.77
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.47
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.54
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 4.05
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 8.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.46
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.54
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.51
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 9.5
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.95
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.05
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 2.29
- Reference cycles: 2.29
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 9.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.06
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.93
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.07
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 7.49
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 17.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.93
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.08
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  35:	02 
  36:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  3d:	02 
  3e:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  45:	02 
  46:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  4d:	02 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 5.02
- Reference cycles: 4.82
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 19.0
- UOPS_MITE: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.9
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.1
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.07
- Reference cycles: 3.89
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.02
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  35:	02 
  36:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  3d:	02 
  3e:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  45:	02 
  46:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  4d:	02 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 4.57
- Reference cycles: 4.36
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 18.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02 
  3f:	62 53 75 48 38 4e 08 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+0x80],0x2
  46:	02 
  47:	62 53 75 48 38 56 09 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+0x90],0x2
  4e:	02 
  4f:	62 53 75 48 38 5e 0a 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+0xa0],0x2
  56:	02 
  57:	62 53 75 48 38 66 0b 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+0xb0],0x2
  5e:	02 
  5f:	62 c3 75 48 38 46 0c 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+0xc0],0x2
  66:	02 
  67:	62 c3 75 48 38 4e 0d 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+0xd0],0x2
  6e:	02 
  6f:	62 c3 75 48 38 56 0e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+0xe0],0x2
  76:	02 
  77:	62 c3 75 48 38 5e 0f 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+0xf0],0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.01
- Reference cycles: 15.57
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.16
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02 
  3f:	62 53 75 48 38 4e 08 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+0x80],0x2
  46:	02 
  47:	62 53 75 48 38 56 09 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+0x90],0x2
  4e:	02 
  4f:	62 53 75 48 38 5e 0a 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+0xa0],0x2
  56:	02 
  57:	62 53 75 48 38 66 0b 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+0xb0],0x2
  5e:	02 
  5f:	62 c3 75 48 38 46 0c 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+0xc0],0x2
  66:	02 
  67:	62 c3 75 48 38 4e 0d 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+0xd0],0x2
  6e:	02 
  6f:	62 c3 75 48 38 56 0e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+0xe0],0x2
  76:	02 
  77:	62 c3 75 48 38 5e 0f 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+0xf0],0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 12.02
- Reference cycles: 11.39
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 15.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.3
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.7
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  35:	02 
  36:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  3d:	02 
  3e:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  45:	02 
  46:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  4d:	02 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 53 75 48 38 4e 08 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+0x80],0x2
  64:	02 
  65:	62 53 75 48 38 56 09 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+0x90],0x2
  6c:	02 
  6d:	62 53 75 48 38 5e 0a 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+0xa0],0x2
  74:	02 
  75:	62 53 75 48 38 66 0b 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+0xb0],0x2
  7c:	02 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 c3 75 48 38 46 0c 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+0xc0],0x2
  93:	02 
  94:	62 c3 75 48 38 4e 0d 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+0xd0],0x2
  9b:	02 
  9c:	62 c3 75 48 38 56 0e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+0xe0],0x2
  a3:	02 
  a4:	62 c3 75 48 38 5e 0f 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+0xf0],0x2
  ab:	02 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 11.02
- Reference cycles: 10.46
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 10.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.31
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 7.69
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  26:	02 
  27:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  2e:	02 
  2f:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  36:	02 
  37:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  3e:	02 
  3f:	62 53 75 48 38 4e 08 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+0x80],0x2
  46:	02 
  47:	62 53 75 48 38 56 09 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+0x90],0x2
  4e:	02 
  4f:	62 53 75 48 38 5e 0a 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+0xa0],0x2
  56:	02 
  57:	62 53 75 48 38 66 0b 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+0xb0],0x2
  5e:	02 
  5f:	62 c3 75 48 38 46 0c 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+0xc0],0x2
  66:	02 
  67:	62 c3 75 48 38 4e 0d 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+0xd0],0x2
  6e:	02 
  6f:	62 c3 75 48 38 56 0e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+0xe0],0x2
  76:	02 
  77:	62 c3 75 48 38 5e 0f 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+0xf0],0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.11
- Reference cycles: 8.13
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.01
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d3 75 48 38 06 02 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14],0x2
   7:	62 d3 75 48 38 56 01 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+0x10],0x2
   e:	02 
   f:	62 d3 75 48 38 5e 02 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+0x20],0x2
  16:	02 
  17:	62 d3 75 48 38 66 03 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+0x30],0x2
  1e:	02 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 d3 75 48 38 6e 04 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+0x40],0x2
  35:	02 
  36:	62 d3 75 48 38 76 05 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+0x50],0x2
  3d:	02 
  3e:	62 d3 75 48 38 7e 06 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+0x60],0x2
  45:	02 
  46:	62 53 75 48 38 46 07 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+0x70],0x2
  4d:	02 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 53 75 48 38 4e 08 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+0x80],0x2
  64:	02 
  65:	62 53 75 48 38 56 09 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+0x90],0x2
  6c:	02 
  6d:	62 53 75 48 38 5e 0a 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+0xa0],0x2
  74:	02 
  75:	62 53 75 48 38 66 0b 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+0xb0],0x2
  7c:	02 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 c3 75 48 38 46 0c 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+0xc0],0x2
  93:	02 
  94:	62 c3 75 48 38 4e 0d 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+0xd0],0x2
  9b:	02 
  9c:	62 c3 75 48 38 56 0e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+0xe0],0x2
  a3:	02 
  a4:	62 c3 75 48 38 5e 0f 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+0xf0],0x2
  ab:	02 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 9.11
- Reference cycles: 8.54
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 36.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.03
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.62
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.62
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.07
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.61
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.39
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.25
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.85
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.71
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.29
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.53
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.48
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   f:	0f 1f 84 00 00 00 00 
  16:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 0.78
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.51
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.48
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   f:	0f 1f 84 00 00 00 00 
  16:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 0.76
- Reference cycles: 0.73
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.77
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.47
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.54
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.14
- Reference cycles: 2.01
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.39
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 9.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.02
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.98
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.05
- Reference cycles: 1.93
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.72
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.02
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 2.29
- Reference cycles: 2.18
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 9.05
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.27
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.93
- UOPS_PORT_1: 0.02
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.07
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.28
- Reference cycles: 4.04
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00 
  32:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  39:	04 02 
  3b:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  42:	05 02 
  44:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  4b:	06 02 
  4d:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  54:	07 02 
  56:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5d:	0f 1f 84 00 00 00 00 
  64:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 4.78
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 19.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.05
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.95
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.07
- Reference cycles: 3.92
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.02
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00 
  32:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  39:	04 02 
  3b:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  42:	05 02 
  44:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  4b:	06 02 
  4d:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  54:	07 02 
  56:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5d:	0f 1f 84 00 00 00 00 
  64:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 4.57
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 18.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02 
  47:	62 13 75 48 38 4c 2e 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  4e:	08 02 
  50:	62 13 75 48 38 54 2e 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  57:	09 02 
  59:	62 13 75 48 38 5c 2e 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  60:	0a 02 
  62:	62 13 75 48 38 64 2e 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  69:	0b 02 
  6b:	62 83 75 48 38 44 2e 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+r13*1+0xc0],0x2
  72:	0c 02 
  74:	62 83 75 48 38 4c 2e 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+r13*1+0xd0],0x2
  7b:	0d 02 
  7d:	62 83 75 48 38 54 2e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+r13*1+0xe0],0x2
  84:	0e 02 
  86:	62 83 75 48 38 5c 2e 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+r13*1+0xf0],0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.01
- Reference cycles: 15.09
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.16
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02 
  47:	62 13 75 48 38 4c 2e 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  4e:	08 02 
  50:	62 13 75 48 38 54 2e 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  57:	09 02 
  59:	62 13 75 48 38 5c 2e 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  60:	0a 02 
  62:	62 13 75 48 38 64 2e 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  69:	0b 02 
  6b:	62 83 75 48 38 44 2e 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+r13*1+0xc0],0x2
  72:	0c 02 
  74:	62 83 75 48 38 4c 2e 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+r13*1+0xd0],0x2
  7b:	0d 02 
  7d:	62 83 75 48 38 54 2e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+r13*1+0xe0],0x2
  84:	0e 02 
  86:	62 83 75 48 38 5c 2e 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+r13*1+0xf0],0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.28
- Reference cycles: 7.88
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.75
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.25
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00 
  32:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  39:	04 02 
  3b:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  42:	05 02 
  44:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  4b:	06 02 
  4d:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  54:	07 02 
  56:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5d:	0f 1f 84 00 00 00 00 
  64:	00 
  65:	62 13 75 48 38 4c 2e 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  6c:	08 02 
  6e:	62 13 75 48 38 54 2e 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  75:	09 02 
  77:	62 13 75 48 38 5c 2e 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  7e:	0a 02 
  80:	62 13 75 48 38 64 2e 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  87:	0b 02 
  89:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  90:	0f 1f 84 00 00 00 00 
  97:	00 
  98:	62 83 75 48 38 44 2e 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+r13*1+0xc0],0x2
  9f:	0c 02 
  a1:	62 83 75 48 38 4c 2e 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+r13*1+0xd0],0x2
  a8:	0d 02 
  aa:	62 83 75 48 38 54 2e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+r13*1+0xe0],0x2
  b1:	0e 02 
  b3:	62 83 75 48 38 5c 2e 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+r13*1+0xf0],0x2
  ba:	0f 02 
  bc:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  c3:	0f 1f 84 00 00 00 00 
  ca:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 9.28
- Reference cycles: 8.81
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  2a:	04 02 
  2c:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  33:	05 02 
  35:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  3c:	06 02 
  3e:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  45:	07 02 
  47:	62 13 75 48 38 4c 2e 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  4e:	08 02 
  50:	62 13 75 48 38 54 2e 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  57:	09 02 
  59:	62 13 75 48 38 5c 2e 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  60:	0a 02 
  62:	62 13 75 48 38 64 2e 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  69:	0b 02 
  6b:	62 83 75 48 38 44 2e 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+r13*1+0xc0],0x2
  72:	0c 02 
  74:	62 83 75 48 38 4c 2e 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+r13*1+0xd0],0x2
  7b:	0d 02 
  7d:	62 83 75 48 38 54 2e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+r13*1+0xe0],0x2
  84:	0e 02 
  86:	62 83 75 48 38 5c 2e 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+r13*1+0xf0],0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.11
- Reference cycles: 7.64
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.99
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.01
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 93 75 48 38 04 2e 	vinserti32x4 zmm0,zmm1,XMMWORD PTR [r14+r13*1],0x2
   7:	02 
   8:	62 93 75 48 38 54 2e 	vinserti32x4 zmm2,zmm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   f:	01 02 
  11:	62 93 75 48 38 5c 2e 	vinserti32x4 zmm3,zmm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  18:	02 02 
  1a:	62 93 75 48 38 64 2e 	vinserti32x4 zmm4,zmm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  21:	03 02 
  23:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  2a:	0f 1f 84 00 00 00 00 
  31:	00 
  32:	62 93 75 48 38 6c 2e 	vinserti32x4 zmm5,zmm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  39:	04 02 
  3b:	62 93 75 48 38 74 2e 	vinserti32x4 zmm6,zmm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  42:	05 02 
  44:	62 93 75 48 38 7c 2e 	vinserti32x4 zmm7,zmm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  4b:	06 02 
  4d:	62 13 75 48 38 44 2e 	vinserti32x4 zmm8,zmm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  54:	07 02 
  56:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5d:	0f 1f 84 00 00 00 00 
  64:	00 
  65:	62 13 75 48 38 4c 2e 	vinserti32x4 zmm9,zmm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  6c:	08 02 
  6e:	62 13 75 48 38 54 2e 	vinserti32x4 zmm10,zmm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  75:	09 02 
  77:	62 13 75 48 38 5c 2e 	vinserti32x4 zmm11,zmm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  7e:	0a 02 
  80:	62 13 75 48 38 64 2e 	vinserti32x4 zmm12,zmm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  87:	0b 02 
  89:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  90:	0f 1f 84 00 00 00 00 
  97:	00 
  98:	62 83 75 48 38 44 2e 	vinserti32x4 zmm16,zmm1,XMMWORD PTR [r14+r13*1+0xc0],0x2
  9f:	0c 02 
  a1:	62 83 75 48 38 4c 2e 	vinserti32x4 zmm17,zmm1,XMMWORD PTR [r14+r13*1+0xd0],0x2
  a8:	0d 02 
  aa:	62 83 75 48 38 54 2e 	vinserti32x4 zmm18,zmm1,XMMWORD PTR [r14+r13*1+0xe0],0x2
  b1:	0e 02 
  b3:	62 83 75 48 38 5c 2e 	vinserti32x4 zmm19,zmm1,XMMWORD PTR [r14+r13*1+0xf0],0x2
  ba:	0f 02 
  bc:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  c3:	0f 1f 84 00 00 00 00 
  ca:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 9.1
- Reference cycles: 9.15
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 36.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.03
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VINSERTI32X4 (ZMM, ZMM, M128, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)