VFMADD231PD (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.79
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 3.79
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.29
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.77
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2
  30:	62 72 f5 48 b8 d2    	vfmadd231pd zmm10,zmm1,zmm2
  36:	62 72 f5 48 b8 da    	vfmadd231pd zmm11,zmm1,zmm2
  3c:	62 72 f5 48 b8 e2    	vfmadd231pd zmm12,zmm1,zmm2
  42:	62 e2 f5 48 b8 c2    	vfmadd231pd zmm16,zmm1,zmm2
  48:	62 e2 f5 48 b8 ca    	vfmadd231pd zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 b8 d2    	vfmadd231pd zmm18,zmm1,zmm2
  54:	62 e2 f5 48 b8 da    	vfmadd231pd zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 b8 e2    	vfmadd231pd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 7.79
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2
  30:	62 72 f5 48 b8 d2    	vfmadd231pd zmm10,zmm1,zmm2
  36:	62 72 f5 48 b8 da    	vfmadd231pd zmm11,zmm1,zmm2
  3c:	62 72 f5 48 b8 e2    	vfmadd231pd zmm12,zmm1,zmm2
  42:	62 e2 f5 48 b8 c2    	vfmadd231pd zmm16,zmm1,zmm2
  48:	62 e2 f5 48 b8 ca    	vfmadd231pd zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 b8 d2    	vfmadd231pd zmm18,zmm1,zmm2
  54:	62 e2 f5 48 b8 da    	vfmadd231pd zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 b8 e2    	vfmadd231pd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 48 b8 c2    	vfmadd231pd zmm0,zmm1,zmm2
   6:	62 f2 f5 48 b8 da    	vfmadd231pd zmm3,zmm1,zmm2
   c:	62 f2 f5 48 b8 e2    	vfmadd231pd zmm4,zmm1,zmm2
  12:	62 f2 f5 48 b8 ea    	vfmadd231pd zmm5,zmm1,zmm2
  18:	62 f2 f5 48 b8 f2    	vfmadd231pd zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 b8 fa    	vfmadd231pd zmm7,zmm1,zmm2
  24:	62 72 f5 48 b8 c2    	vfmadd231pd zmm8,zmm1,zmm2
  2a:	62 72 f5 48 b8 ca    	vfmadd231pd zmm9,zmm1,zmm2
  30:	62 72 f5 48 b8 d2    	vfmadd231pd zmm10,zmm1,zmm2
  36:	62 72 f5 48 b8 da    	vfmadd231pd zmm11,zmm1,zmm2
  3c:	62 72 f5 48 b8 e2    	vfmadd231pd zmm12,zmm1,zmm2
  42:	62 e2 f5 48 b8 c2    	vfmadd231pd zmm16,zmm1,zmm2
  48:	62 e2 f5 48 b8 ca    	vfmadd231pd zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 b8 d2    	vfmadd231pd zmm18,zmm1,zmm2
  54:	62 e2 f5 48 b8 da    	vfmadd231pd zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 b8 e2    	vfmadd231pd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 4.01
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 3.79
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7
  30:	62 52 bd 48 b8 c0    	vfmadd231pd zmm8,zmm8,zmm8
  36:	62 52 b5 48 b8 c9    	vfmadd231pd zmm9,zmm9,zmm9
  3c:	62 52 ad 48 b8 d2    	vfmadd231pd zmm10,zmm10,zmm10
  42:	62 52 a5 48 b8 db    	vfmadd231pd zmm11,zmm11,zmm11
  48:	62 52 9d 48 b8 e4    	vfmadd231pd zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 b8 c0    	vfmadd231pd zmm16,zmm16,zmm16
  54:	62 a2 f5 40 b8 c9    	vfmadd231pd zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 b8 d2    	vfmadd231pd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 8.27
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7
  30:	62 52 bd 48 b8 c0    	vfmadd231pd zmm8,zmm8,zmm8
  36:	62 52 b5 48 b8 c9    	vfmadd231pd zmm9,zmm9,zmm9
  3c:	62 52 ad 48 b8 d2    	vfmadd231pd zmm10,zmm10,zmm10
  42:	62 52 a5 48 b8 db    	vfmadd231pd zmm11,zmm11,zmm11
  48:	62 52 9d 48 b8 e4    	vfmadd231pd zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 b8 c0    	vfmadd231pd zmm16,zmm16,zmm16
  54:	62 a2 f5 40 b8 c9    	vfmadd231pd zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 b8 d2    	vfmadd231pd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 48 b8 c0    	vfmadd231pd zmm0,zmm0,zmm0
   6:	62 f2 f5 48 b8 c9    	vfmadd231pd zmm1,zmm1,zmm1
   c:	62 f2 ed 48 b8 d2    	vfmadd231pd zmm2,zmm2,zmm2
  12:	62 f2 e5 48 b8 db    	vfmadd231pd zmm3,zmm3,zmm3
  18:	62 f2 dd 48 b8 e4    	vfmadd231pd zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 b8 ed    	vfmadd231pd zmm5,zmm5,zmm5
  24:	62 f2 cd 48 b8 f6    	vfmadd231pd zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 b8 ff    	vfmadd231pd zmm7,zmm7,zmm7
  30:	62 52 bd 48 b8 c0    	vfmadd231pd zmm8,zmm8,zmm8
  36:	62 52 b5 48 b8 c9    	vfmadd231pd zmm9,zmm9,zmm9
  3c:	62 52 ad 48 b8 d2    	vfmadd231pd zmm10,zmm10,zmm10
  42:	62 52 a5 48 b8 db    	vfmadd231pd zmm11,zmm11,zmm11
  48:	62 52 9d 48 b8 e4    	vfmadd231pd zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 b8 c0    	vfmadd231pd zmm16,zmm16,zmm16
  54:	62 a2 f5 40 b8 c9    	vfmadd231pd zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 b8 d2    	vfmadd231pd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VFMADD231PD (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10